Figure 4-10. Rgmii1 Gigabit Ethernet Phy Strapping Resistors; Table 4-4. Rgmii1 Gigabit Ethernet Phy Strapping Resistors - Texas Instruments AM263 Series User Manual

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The Ethernet PHY requires three separate power sources. VDDIO is the 3.3V, system generated supply. There
are dedicated LDO's for the 1.1V and 2.5V supplies for the Ethernet PHY.
There are series termination resistors on the transmit and receive clock signals located near the AM263x SoC.
The MDIO and Interrupt signals from the SoC to the PHY require 2.2KΩ pull up resistors to the I/O supply
voltage for proper operation. The interrupt signal is driven by a GPIO signal that is mapped from the AM263x
SoC.
The reset signal for the Ethernet PHY is driven by a 2-input AND gate. The AND gate's inputs are a GPIO signal
that is generated by the IO Expander and PORz.
The Ethernet PHY uses many functional pins as strap option to place the device into specific modes of
operation.

Figure 4-10. RGMII1 Gigabit Ethernet PHY Strapping Resistors

RX_D0 and RX_D1 are open rather than pulled down with 2.49KΩ resistors because they are on a
4-level strap resistor mode scheme. All other signals are 2-level strap resistor modes.
Each strapping has an internal pull down resistance of 9KΩ.

Table 4-4. RGMII1 Gigabit Ethernet PHY Strapping Resistors

Functional Pin
RX_D0
RX_D1
JTAG_TDO/GPIO_1
RX_D3
RX_D2
LED_0
RX_ER
LED_2
RX_DV
SPRUJ09C – MARCH 2022 – REVISED FEBRUARY 2023
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Note
Note
Default Mode Mode in CC
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Copyright © 2023 Texas Instruments Incorporated
Function
PHY address: 0000
RGMII to Copper
Auto-negotiation, 1000/100/10 advertised, auto MDI-X
Port Mirroring Disabled
AM263x Control Card Hardware User's Guide
Hardware Description
23