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28
Pin Name
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
Note:
1.
During ramp-up of the VDDAN_33 power rail, all GPIOs are undefined and a voltage bump may
appear momentarily (less than 200 mV).
2.
Internal PU or PD is effective after VDDCR_SOC is at ready state. Before VDDCR_SOC is ready, the
GPIOs are of Hi-Z state.
3.
All GPIOs are configured as input by default after VDDCR_SOC is at ready state. GPIOs can be
programmed as output by the video BIOS or driver.
4.
For GPIOs that serve as pin straps, any external circuits using them must not conflict with the logic
level required by the strap after power up until PCIe reset gets de-asserted.
5.
See
"Vega 10" Databook
56006_1.00
Type
I/O
3.3V
(VDDAN_33)
I/O
3.3V
(VDDAN_33)
I/O
3.3V
(VDDAN_33)
I/O
3.3V
(VDDAN_33)
I/O
3.3V
(VDDAN_33)
I/O
3.3V
(VDDAN_33)
I/O
3.3V
(VDDAN_33)
I/O
3.3V
(VDDAN_33)
I/O
3.3V
(VDDAN_33)
Configuration Straps (p. 37)
PD/PU
Description
PD-reset General purpose I/O and pin strap.
See
Table 3–24 (p. 38)
PD-reset General purpose I/O and pin strap.
See
Table 3–24 (p. 38)
PD-reset General purpose I/O.
PD-reset General purpose I/O and pin strap.
See
Table 3–24 (p. 38)
PD-reset General purpose I/O and pin strap.
See
Table 3–24 (p. 38)
PD-reset General purpose I/O and pin strap.
See
Table 3–24 (p. 38)
PD-reset General purpose I/O and pin strap.
Can be unconnected if not used.
See
Table 3–24 (p. 38)
PD-reset General purpose I/O and pin strap.
See
Table 3–24 (p. 38)
PD-reset Do not connect on the PCB. Provide a test pad.
for more information on pin strap configurations.
Signal Descriptions
for pin strap definition.
for pin strap definition.
for pin strap definition.
for pin strap definition.
for pin strap definition.
for pin strap definition
for pin strap definition.
© 2017 Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
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