AMD Vega 10 Data Book page 9

Chapter 1 Introduction
Figure 1-1 "Vega 10" Branding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 2 Functional Overview
Figure 2-1 "Vega 10" Display Top-level Data-flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 4 Timing Specifications
Figure 4-1 SMBus Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 4-2 SMBus Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 4-3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 4-4 Serial Flash Write/Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 4-5 eDP Panel Power-up/down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 4-6 Backlight PWM Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Chapter 5 Electrical Characteristics
Figure 5-1 Load Insertion Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 5-2 Load Release Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Chapter 7 Mechanical Data
Figure 7-1 "Vega 10" Package Outline (Preliminary-MOD-00370 REV 01) . . . . . . . . . . . . . . . . . 70
Figure 7-2 "Vega 10" Package Outline (Preliminary-MOD-00370 REV 01) Top View . . . . . . . . . 71
Figure 7-3 "Vega 10" Ball Names (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 7-4 FCBGA Reference Reflow Profile for RoHS/Lead-Free SMT . . . . . . . . . . . . . . . . . . . . . . . 74
Chapter 8 Boundary Scan Specification
Figure 8-1 Timing of the Boundary Scan Signals with Respect to TCK . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 8-2 Timing of the TAP Ports (TDI, TMS, and TDO) with Respect to TCK . . . . . . . . . . . . . . . . 78
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Figures
"Vega 10" Databook
56006_1.00