Table of Contents
Advertisement
Timing Specifications
3.
PERSTB is deasserted, and pin-strap settings are latched permanently into the
device (until PERSTB is asserted again, or the power is removed).
4.
In parallel:
Note: The system may not issue a configuration transaction to the device until
the device internal reset sequence is complete.
5.
For an add-in card implementation, the device completes reading the "ROM
straps."
6.
Device internal reset is complete. The system begins enumerating the devices
attached to it by issuing configuration transactions.
7.
The chip responds to any pending transaction requests, and the system
continues PCI Express® enumeration, which sets up the configuration registers
of the device.
8.
The system copies the contents of the ROM into system memory, and executes
the video BIOS, completing the device initialization. This occurs before POST
begins in the system BIOS, based on the PC 98 System Design Guide.
The device is ready for normal operation.
There are three configurations for strap/BIOS implementation:
Configuration 1. The controller is located on an add-in card, and there is access to
a local video BIOS serial flash memory.
The ROM state machine of "Vega 10" will read in all the "ROM-based straps" right
after PERSTB reset is deasserted. There are a total of 33 DWORDs of "ROM-based
straps" which are stored at byte locations 0x70 through 0xF4 in the serial flash
memory. See
For "Vega 10", security features have been implemented to block access to the ROM
when a fuse is set. After this, when the ROM needs to be accessed, external software
will have to message the SMU firmware which will authenticate the new ROM
contents and write it out.
Configuration 2. The controller is located on the system motherboard and the video
BIOS is stored in the system BIOS serial-flash memory (i.e., no dedicated ROM for
the video BIOS).
The system BIOS will be responsible for loading the SUBSYSTEM_ID and
SUBSYSTEM_VENDOR_ID through an aliased address in the controller chip's
configuration space. The reason for writing through an aliased address (16#4c) is
that the configuration location 16#2c is read only. Any writes to this location (16#4c)
will also change the content of the SUBSYSTEM_VENDOR_ID at 16#2c.
Configuration 3. A combination of configurations 1 and 2 (add-in card and device
on the motherboard)
The system BIOS will take care of the graphics device on the motherboard as in case
2, while the chip on the add-in board will be taken care of as in case 1. This should
cover the situation where the OS does not read the add-in card's video BIOS because
the ROM state machine from the graphics chip reads the "ROM-based straps"
independently from the video BIOS.
© 2017 Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
a.
The device begins to read "eFuse straps."
b.
If a ROM exists (and is programmed), the device begins to read "ROM
straps" from its external ROM.
Table 3–25 (p. 41)
for details.
49
"Vega 10" Databook
56006_1.00
Advertisement
Table of Contents
