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XDV-P9
Pin No.
Pin Name
63
/DMOUT
64
/CKSE
65
/DACT
66
TESIN
67
TESIO1
68
VSS
69
PXI
70
PXO
71
VDD
72
XVSS
73
XI
74
XO
75
XVDD
76
DVDD
77
RO
78
DVSS
79
DVR
80
LO
81
DVDD
82-84
TEST1-3
85-88
BUS0-3
89
VDD
90
VSS
91
BUCK
92
/CCE
93
TEST4
94
/TSMOD
95
/RST
96
TEST0
97
/HSO
98
/UHSO
99
EMPH
100
LRCK
*TC9461F
51
75
94
I/O
Function and Operation
I
A terminal for setting the mode to output binary PWM for a feed equalizer
from I/O terminals 0 and 1, and binary PWM for disc equalizer from I/O
terminal 2 and 3
I
X'tal select terminal
I
Test terminal
I
Test input terminal
I
Test input/output terminal
Digital GND
I
DSP group clock oscillation circuit input terminal
O
DSP group clock oscillation circuit input terminal
Digital power supply terminal
Ground terminal for system clock oscillation circuit
I
System clock oscillation circuit input terminal
O
System clock oscillation circuit output terminal
Power supply terminal for system clock oscillation circuit
D/A converter power supply terminal
O
R channel data positive rotation output terminal
D/A converter analog ground terminal
D/A converter reference voltage terminal
O
L channel data positive rotation output terminal
D/A converter power supply terminal
I
Test terminal
I/O
Data input/output terminal for microcomputer interface
Digital power supply terminal
Digital GND
I
Clock input terminal for microcomputer interface
I
Chip enable signal input terminal for microcomputer interface
I
Test terminal
I
Local test mode select terminal
I
Reset signal input terminal
I
Test terminal
O
Play speed mode flag output terminal
O
/UHSO /HSO
H
H
L
L
O
Emphasis flag output terminal of subcode Q data
O
Channel clock (44.1 kHz) output terminal
25
1
Play speed
H
Once speed play
L
Twice speed play
H
Four times speed play
L
Eight times speed play
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