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- Pin Functions (PD4995A)
Pin No.
Pin Name
1,2
GND
3
NC
4
DXTLI
5
DXTLO
6
BUNRI
7
TSTSTB
8
PC2/STB
9
PC3/BSYNC
10
PC4/SELNED
11
PA7/NED7
12
PA6/NED6
13
PA5/NED5
14
PA4/NED4
15
VDD
16
GND
17
PA3/NED3
18
PA2/NED2
19
PA1/NED1
20
PA0/NED0
21
BMODE1
22-25
DD7-4
26
GND
27
VDD
28-31
DD3-0
32
XDCAS
33
XDWE
34
XDOE
35
XDRAS
36-38
DA12-10
39-41
DA9-7
42
GND
43
VDD
44-50
DA6-0
51,52
GND
53
VDD
54
XWR
55
XSACK
56
SREQ
57-60
SDATA0-3
61
GND
62
VDD
63-66
SDATA4-7
67
XAVTRM
68
BMODE2
69
DMACKI
70
GND
71
DMACKO
72
XSCL1
73
XSWAIT
74
XSRD
75
XSWR
76
XSDREQ
77
SDACK
78
VDD
79
GND
80-91
SA11-0
92-95
SAD7-4
96
VDD
97
GND
98-101
SAD3-0
I/O
Function and Operation
Digital circuit GND
Not used
I
27MHz crystal connection terminal which oscillates reference clock signals of
the spindle and PLL
O
Not used
I
Separation test control terminal for internal RAM
I
Test mode setting input
I/O
Not used
I/O
Not used
I
I/O setting terminals for NED (7:0), STM and BSYNC terminals
I/O
Not used
I/O
Not used
I/O
Not used
I/O
Not used
Digital circuit power supply
Digital circuit GND
I/O
Not used
I/O
Not used
I/O
Not used
I/O
Not used
I
Sets which test is done in the test mode
I/O
DRAM data bus for VBR buffer
Digital circuit GND
Digital circuit power supply
I/O
DRAM data bus for VBR buffer
O
DRAM CAS signal for VBR buffer
O
DRAM WE signal for VBR buffer
O
DRAM OE signal for VBR buffer
O
DRAM RAS signal for VBR buffer
O
Not used
O
DRAM address signal for VBR buffer
Digital circuit GND
Digital circuit power supply
O
DRAM address signal for VBR buffer
Digital circuit GND
Digital circuit power supply
O
Not used
O
Transfer response terminal for VIDEO_DMA channel
I
Data transfer request terminal for VIDEO_DMA channel
O
Data output bus for VIDEO=DMA channel
Digital circuit GND
Digital circuit power supply
O
Data output bus for VIDEO=DMA channel
O
Signal indicating the head of the sector of the transfer data for VIDEO_DMA
channel
I
Sets which test is done in the test mode
I
System clock input of DVD/CD ROM data
Digital circuit GND
O
Outputs reference crystal clock signals of the spindle and PLL
I
Chip select signal from the main CPU
O
WAIT output to the main CPU
I
RD signal for the main CPU
I
WR signal for the main CPU
O
DMA request for the main CPU
I
DMA response signal
Digital circuit power supply
Digital circuit GND
I
Main CPU address
I/O
Main CPU data bus
Digital circuit power supply
Digital circuit GND
I/O
Main CPU data bus
XDV-P9
107
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