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XDV-P9
Pin No.
Pin Name
102,103
XIRQ10,11
104
VDD
105,106
GND
107
CKCD
108
DIFOUT
109
BCK
110
LRCK
111
ADATAO
112
CDDT
113
CDLR
114
CDBCK
115
CDDO
116
C2FI
117
WFCK
118
SCOR
119
SBSO
120
EXCK
121
VDD
122
GND
123
DSPA0
124
DSPA1
125
DSPA2
126
ASDATA0/PB0
127
ASDATA1/PB1
128
ASDATA2/PB2
129
ASDATA3/PB3
130
VDD
131
GND
132
ASDATA4/PB4
133
ASDATA5/PB5
134
ASDATA6/PB6
135
ASDATA7/PB7
136
XAWR
137
ASREQ
138
TMC2
139
ASTB
140
XMCS
141
XIRQ2
142
XMWR
143
XMRD
144
MAD7/PE7
145
MAD6/PE6
146
MAD5/PE5
147
MAD4/SA16/PE4
148
GND
149
VDD
150
MAD3/SA15/PE3
151
MAD2/SA14/PE2
152
MAD1/SA13/PE1
153
MAD0/SA12/PE0
154
RPWM
155,156
GND
157
VDD
158
RERR
159
FPWM
160
VPWM
161
PPWM
162
FGPL
163
XASACK
108
I/O
Function and Operation
O
Interrupt request for the main CPU
Digital circuit power supply
Digital circuit GND
I
Master clock of audio I/F block
O
Digital audio output
O
Bit clock output to DAC
O
LRCK signal output to DAC
O
Serial data output to DAC
I
Audio data input from CD decoder
I
LRCK signal input from CD decoder
I
Bit clock input from CD decoder
I
Digital out signal input from CD decoder
I
Input terminal for the C2 error flag from CD decoder
I
CD frame clock signal
I
CD subcode sync input terminal
I
CD subcode data input terminal
O
Shift clock which generates the timing at which data is sent to the SBSO
terminal
Digital circuit power supply
Digital circuit GND
O
Not used
O
Not used
O
Not used
I/O
Not used
I/O
Not used
I/O
Not used
I/O
Not used
Digital circuit power supply
Digital circuit GND
I/O
Not used
I/O
Not used
I/O
Not used
I/O
Not used
O
Not used
I
Transfer request terminal for AUDIO_DMA channel
I
Terminal test control terminal
I
Strobe signal indicating that address information is provided in the address
data bus (7:0) of the sub CPU
I
Chip select signal from the sub CPU
O
Interrupt request for the sub CPU
I
Sub CPU WR signal
I
Sub CPU RD signal
I/O
Connected to the multiplex bus of the sub CPU address data
I/O
Connected to the multiplex bus of the sub CPU address data
I/O
Connected to the multiplex bus of the sub CPU address data
I/O
Connected to the multiplex bus of the sub CPU address data
Digital circuit GND
Digital circuit power supply
I/O
Connected to the multiplex bus of the sub CPU address data
I/O
Connected to the multiplex bus of the sub CPU address data
I/O
Connected to the multiplex bus of the sub CPU address data
I/O
Connected to the multiplex bus of the sub CPU address data
O
Not used
Digital circuit GND
Digital circuit power supply
O
Control output for rough servo
O
7-bit PWM output terminal for FG servo
O
5-bit PWM output terminal for velocity servo
O
PWM output terminal for phase servo
I
Rotational pulse input from the spindle motor
O
Not used
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