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ADDR=0x174: Receive Path Delta
Bit 7
Bit 6
Bit name Reserved
Reserved
R/W
—
—
Value
0
0
after
reset
Bits 7-5: Reserved
Bit 4:
RX_C2_D: RX_C2 delta bit. It is set when a new value is stored in RX_G1 [2:0].
Bit 3:
RX_G1_D: RX_G1 delta bit. It is set when RX_UNEQ changes state.
Bit 2:
RX_UNEQ_D: RX_UNEQ delta bit. It is set when RX_PLM changes state.
Bit 1:
RX_PLM_D: RX_PLM delta bit. It is set when a new value is stored in RX_C2 [7:0]
Bit 0:
Reserved
Write one to these bits to clear them.
ADDR=0x176: Expected C2 Byte
Bit 7
Bit 6
Bit name EXP_C2 [7:0]
R/W
R/W
Value
0
0
after
reset
Bits 7-0: EXP_C2 [7:0]
The received C2 bytes are monitored so that reception of the correct type of payload can be verified. When
a consistent C2 value is received for five consecutive frames, it is written to RX_C2 [7:0], and the RX_C2_D
delta bit is set. The expected value of the received C2 bytes is provided in EXP_C2 [7:0]. Its value after
reset is 0x18 which indicates the mapping of a LAPS framed signal. If the received value does not match the
expected value, and it is NOT:
• all zeros unequipped label
• 0x01 equipped, non-specific label
• 0xFC payload defect label
• 0xFF reserved label
then the Payload Label Mismatch register bit, RX_PLM, is set to one.
If the current accepted value is the all zeros unequipped label, and EXP_C2[7:0]
unequipped register bit, RX_UNEQ, is set to one.
76
Bit 5
Bit 4
Reserved
RX_C2_D
—
W1C
0
0
Bit 5
Bit 4
0
1
Bit 3
Bit 2
RX_G1_D
RX_UNEQ_
D
W1C
W1C
0
0
Bit 3
Bit 2
1
0
Bit 1
Bit 0
RX_PLM_D
Reserved
W1C
—
0
—
Bit 1
Bit 0
0
0
0, then the
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