Agilent Technologies HDMP-3001 Datasheet page 73

ADDR=0x12F: Receive RDI Monitor
Bit 7 Bit 6
Bit name G1_CONSEC_NUM[3:0]
R/W R/W
Value 0 1
after
reset
Bits 7-4: G1_CONSEC_NUM [3:0]: These 4 bit registers specify the number of consecutive received G1
bytes which will be monitored to determine if a Path RDI indication is present.
Bits 3-1: Reserved
Bit 0: RX_PRDI5: It is used to determine which bits of the G1 byte will be monitored for Path RDI
indication. If set, the HDMP-3001 will use only bit 5 of the received G1 byte. If not, bits 5,6, and 7 of
the received G1 byte will be used.
ADDR=0x130: Receive J1 Delta
Bit 7 Bit 6
Bit name Reserved Reserved
R/W — —
Value 0 0
after
reset
Bits 7-3: Reserved
Bit 2: J1_AVL_D: It is set when J1 capture is completed. It is cleared when writing a one to it.
Bit 1: Reserved
Bit 0: J1_OOF_D: It is set when J1_OOF changes state. It is cleared when writing a one to it.
73
Bit 5 Bit 4
0 1
Bit 5 Bit 4
Reserved Reserved
— —
0 0
Bit 3 Bit 2
Reserved Reserved
— —
0 0
Bit 3 Bit 2
Reserved J1_AVL_D
— W1C
0 0
Bit 1 Bit 0
Reserved RX_PRDI5
— R/W
0 0
Bit 1 Bit 0
Reserved J1_OOF_D
— W1C
0 0