Agilent Technologies HDMP-3001 Datasheet page 11

Ethernet over sonet mapper ic device specification
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Signal name
TX_E1_DATA
TX_E2_DATA
TX_F1_DATA
TX_E1E2F1_CLK
TX_LDCC_DATA
TX_LDCC_CLK
TX_SDCC_DATA
TX_SDCC_CLK
TX_8K_CLK
11
Pin #
Type(I/O)
Signal description
126
I
TRANSMIT E1 DATA: Local orderwire channel data byte
(E1) to be inserted by the HDMP-3001 into the outgoing
SONET data stream.
127
I
TRANSMIT E2 DATA: Express orderwire channel data byte
(E2) to be inserted by the HDMP-3001 into the outgoing
SONET data stream.
128
I
TRANSMIT F1 DATA: Maintenance channel data byte (F1)
to be inserted by the HDMP-3001 into the outgoing SONET
data stream.
129
O
TRANSMIT E1/E2/F1 DATA REFERENCE CLOCK: A 64 kHz clock
reference output for E1/E2/F1 data to be inserted by the
HDMP-3001 into the outgoing SONET data stream.
123
I
TRANSMIT LINE DCC DATA: Input for the Line Data
Communications Channel (DCC) to be inserted by the HDMP-3001
into the outgoing SONET data stream.
124
O
TRANSMIT LINE DCC REFERENCE CLOCK: A 576 kHz clock
reference for Line DCC data to be inserted by the
HDMP-3001 into the outgoing SONET data stream. The
TX_LDCC_DATA inputs are sampled on the falling edge of
TX_LDCC_CLK.
117
I
TRANSMIT SECTION DCC DATA: Input for the Section
Data Communications Channel (DCC) to be inserted into the
outgoing SONET data stream from the HDMP-3001.
118
O
TRANSMIT SECTION DCC REFERENCE CLOCK:
A 192 kHz clock reference for Section DCC data to be inserted
by the HDMP-3001 into the outgoing SONET data stream. The
TX_SDCC_DATA inputs are sampled on the falling edge of
TX_LDCC_CLK.
132
O
8kHz TRANSMIT CLOCK: A general purpose 8kHz
buffered clock derived from TX_SONETCLK which may be
used for external clock reference purposes.

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