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ADDR=0x131: Receive J1 Mask
Bit 7
Bit 6
Bit name Reserved
Reserved
R/W
—
—
Value
0
0
after
reset
Bits 7-2: Reserved
Bit 1:
J1_AVL_MASK: J1_AVL mask bit.
Bit 0:
J1_OOF_D_MASK: J1_OOF delta bit mask.
These bits are used to enable/disable status reporting of the corresponding event bits. If set, the status
reporting of the corresponding event bits is disabled.
ADDR=0x132: Receive POH Mask
Bit 7
Bit 6
Bit name Reserved
Reserved
R/W
—
—
Value
0
0
after
reset
Bits 7-5: Reserved
Bit 4:
RX_C2_D_MASK: RX_C2 delta bit mask.
Bit 3:
RX_G1_D_MASK: RX_G1 delta bit mask.
Bit 2:
RX_UNEQ_D_MASK: RX_UNEQ delta bit mask.
Bit 1:
RX_PLM_D_MASK: RX_PLM delta bit mask.
Bit 0:
Reserved
These bits are used to enable/disable status reporting of the corresponding event bits. If set, the status
reporting of the corresponding event bits is disabled.
74
Bit 5
Bit 4
Reserved
Reserved
—
—
0
0
Bit 5
Bit 4
Reserved
RX_C2_D_ RX_G1_D_
MASK
—
R/W
0
1
Bit 3
Bit 2
Reserved
Reserved
—
—
0
0
Bit 3
Bit 2
RX_UNEQ_
MASK
D_MASK
R/W
R/W
1
1
Bit 1
Bit 0
J1_AVL_
J1_OOF_D_
MASK
MASK
R/W
R/W
1
1
Bit 1
Bit 0
RX_PLM_D
Reserved
_MASK
R/W
—
1
0
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