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ADDR=0x0FC: Receive LOH Monitor Masks
Bit 7
Bit 6
Bit name J0_OOF_
Reserved
D_MASK
R/W
R/W
—
Value
1
1
reset
Bit 7:
J0_OOF_D_MASK – J0_OOF delta bit mask
Bit 6:
Reserved, always write as one.
Bit 5:
RX_LAIS_D_MASK – RX_LAIS delta bit mask
Bit 4:
RX_LRDI_D_MASK – RX_LRDI delta bit mask
Bit 3:
RX_K1_D_MASK – RX_K1 delta bit mask
Bit 2:
K1_UNSTAB_D_MASK – K1_UNSTAB delta bit mask
Bit 1:
RX_K2_D_MASK – RX_K2 delta bit mask
Bit 0:
Reserved, always write as one.
These bits are used to enable/disable reporting status of the corresponding event bits. If set, reporting status
of the corresponding event bits is disabled.
ADDR=0x0FD: Receive SOH Monitor Masks
Bit 7
Bit 6
Bit name Reserved
Reserved
R/W
—
—
Value
0
0
after
reset
Bits 7-6: Reserved
Bit 5:
RX_LOS_D_MASK – RX_LOS delta bit mask
Bit 4:
Reserved
Bit 3:
RX_OOF_D_MASK – RX_OOF delta bit mask
Bit 2:
RX_LOF_D_MASK – RX_LOF delta bit mask
Bits 1-0: Reserved
These bits are used to enable/disable reporting status of the corresponding event bits. If set, reporting status
of the corresponding event bits is disabled.
62
Bit 5
Bit 4
RX_LAIS_
RX_LRDI_ RX_K1_D
D_MASK
D_MASK
R/W
R/W
1
1
Bit 5
Bit 4
RX_LOS_D Reserved
_MASK
R/W
—
1
0
Bit 3
Bit 2
K1_UNSTAB
_MASK
_D_MASK
R/W
R/W
1
1
Bit 3
Bit 2
RX_OOF_D
RX_LOF_D_
_MASK
_MASK
R/W
R/W
1
1
Bit 1
Bit 0
RX_K2_D
Reserved
_MASK
R/W
—
1
1
Bit 1
Bit 0
Reserved
Reserved
—
—
0
0
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