Dram Timing Settings - JETWAY 693AS User Manual

3-6-1 DRAM Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
Auto Configuration
RAS Precharge Time
RAS Active Time
Activate to Command Delay
CAS Latency
Bank Interleave
DRAM Drive Control
Delay DRAM Read Latch
Memory Data Drive
SDRAM Command Drive
↑↓→← Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: Auto, 2 and 3.
Activate To Command Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: Auto, 2T and 3T.
RAS Active Time
Select the number of SCLKs for an access cycle. The settings are: Auto, 5T and 6T.
CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2 and 3.
DRAM Drive Control
This field let's you choose the Memory Address, Memory Data drive current to suit your
SDRAM Module, the Default setting is Auto.
DRAM Timing Settings
Standard
3T
6T
3T
Auto
Auto
Auto
0.5ns
Normal
Weak
F6:Optimized Defaults
30
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F7:Standard Defaults