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HperTransport Width
The default setting is "Auto" for this selection, and it provides with the adjustable bandwidth
selection for you to choose the combination of stream with x16 and x8 bandwidth of updoad
and down between the processor and system chip.
DRAM Timing Settings
Please refer to section 3-6-1
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
3-6-1 DRAM Timing Settings
Auto Configuartion
DRAM CAS Latency
SDRAM Cycle Time
SDRAM RAS-to-CAS Delay
SDRAM Precharge Time
DRAM Command Rate
MTRR Mapping Mode
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
SDRAM RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 4T and 3T.
SDRAM Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Settings
Auto
2.5T
8T
4T
2T
2T
Continuous
F6:Optimized Defaults
Menu Level >>
F7:Standard Defaults
27
Item Help
F1:General Help
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