Furuno FS-1570 Service Manual page 135

Pin No. Order of
W/R1
& Name execution
U502
#15 QA 1
#1 QB 2
#2 QC 3
U504
#3 QD 4
#4 QE 5
#5 QF 6
#6 QG 7
#7 QH 8
#16 Q1 9
#15 Q2 10
#14 Q3 11
U503 #13 Q4 12
#12 Q5 13
#11 Q6 14
#10 Q7 15
#9 Q8 16
Control signals generated by Data 3 on W/R 2 board are the same as those on
W/R 1 board.
Table 5.3.6 Signals generated by DATA 2 on W/R1 board
Signal name
PLL data
DDS2 LOAD A
DDS1 LOAD B
U503 ST
(NOR: ST CONT2)
U502 ST
(NOR: ST CONT2)
N.C
N.C
N.C
N.C
BAND-1
BAND-2
BAND-3
BAND-4
H/L
TEST
LPF 1
LPF 2
5-18
5.3 T-CPU board (05P0732)
Function
PLL data for PLL IC (U502)
LOAD signal for U506
kHz)
LOAD signal for U501 (DDS1, 6 MHz
PLL Ref)
Used to generate latch signal for U503
by NOR gate ST CONT2 signal
Used to generate latch signal for U502
by NOR gate ST CONT2 signal
PLL BAND selection (1.6 to 6 MHz)
PLL BAND selection (6 to 13.5 MHz)
PLL BAND selection
(13.5 to 21.5 MHz)
PLL BAND selection
(21.5 to 27.5 MHz)
Divides each band into 2 bands
Outputs W/R-1 self-test signal (18 MHz)
RF filter selection (1.6 to 13.2 MHz)
RF filter selection (13.2 to 27.5 MHz)
(DDS2, 456.7