JVC XV-M565BK Service Manual page 58

XV-M565BK/M567GD
Symbol
I/O
Pin No.
99 MADDR8 O
100 MADDR10
101 E VDD -
102 MADDR 7 O
103 E VSS -
104 MADDR 0
105 MADDR 6 O
106 MADDR 1
107 E VDD -
108 MADDR 5 O
109 E VSS -
110 MADDR 2
111 MADDR 4 O
112 MADDR 3
113 E VDD -
114 MADDR 12 -
115 E VSS -
116 MADDR 13 -
117 i vdd -
118 MADDR 14 -
119 i vss -
120 MADDR 15 -
121 MADDR 16 -
122 MADDR 17 -
123 E VDD -
124 MADDR 18 -
125 E VSS -
126 MADDR 19 -
127 MADDR 20 -
128 ROM CS -
129 TEST PIN2 I/O
130 OSD CLK -
131 OSD DATA0 -
132 OSD DATA1 -
133 TEST PIN3 I/O
134 E VDD -
135 OSD DATA2 -
136 E VSS -
137 OSD DATA3 -
138 TEST PIN4 I/O
139 OSD BLK1 -
140 OSD VC1 -
141 TEST PIN5 I/O
142 VDATA0 O
143 VDATA1
144 i vdd -
145 VDATA2 O
146 i vss -
147 TEST PIN6 I/O
148 VDATA3 O
1-58
Function
Memory address.
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for I/O signals.
Connected to TP513
Ground for core logic and I/O signals.
Connected to TP514
2.5-V supply voltage for core logic.
Connected to TP515
Ground for core logic and I/O signals.
Connected to TP516
Connected to TP517
Connected to TP518
3.3-V supply voltage for I/O signals.
Connected to TP519
Ground for core logic and I/O signals.
Connected to TP520
Connected to TP521
Connected to TP522
Programmable I/O pins. Input mode after reset.
Connected to TP523
Connected to TP525
Connected to TP526
Programmable I/O pins. Input mode after reset.
3.3-V supply voltage for I/O signals.
Connected to TP528
Ground for core logic and I/O signals.
Connected to TP529
Programmable I/O pins. Input mode after reset.
Connected to TP531
Connected to TP532
Programmable I/O pins.Input mode after reset.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up,
the decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA
2.5-V supply voltage for core logic.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up,
the decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA
Ground for core logic and I/O signals.
Programmable I/O pins. Input mode after reset.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up,
the decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA
ZIVA3-PEO (3/5)