JVC XV-M565BK Service Manual page 52

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XV-M565BK/M567GD
Pin NO.
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
1-52
Symbol
I/O
CPUADR10
I
CPUADR9
I
CPUADR8
I
CPUADR7
I
CPUADR6
I
CPUADR5
I
CPUADR4
I
CPUADR3
I
CPUADR2
I
CPUADR1
I
VSS
CPUADR0
I
NCS
I
NWR
I
NRD
I
VDD
CPUDT7
CPUDT6
PVPPDRAM
O
PTESTDRAM
I
PVDDDRAM
PVSSDRAM
CPUDT5
CPUDT4
CPUDT3
VSS
CPUDT2
CPUDT1
I/O
CPUDT0
I/O
CLKOUT1
O
VDD
-
TEHLD
O
DTRO
O
IDGT
O
BDO
I
CPDET2
I
CPDET1
I
VSS
MMOD
I
NRST
I
VDD
-
CLKOUT2
O
PLLOK
O
IDHOLD
O
JMPINH
O
Function
System control address
System control address
System control address
System control address
System control address
System control address
System control address
System control address
System control address
System control address
GND
System control address
System control chip select
System control write
System control read
Apply 3V
System control data
System control data
C=10000PF is connected between VSS
VSS connected
System control data
System control data
System control data
GND
System control data
System control data
System control data
16.9/11.2/8.45MHz clock
Apply 3V
Mirror gate
Data part frequency control switch
Part CAPA switch
RF dropout / BCA data of making to binary
Outer side CAPA detection
Side of surroundings on inside
GND
VSS connected
System reset
Apply 3V
16.9MHz clock
Frame mark detection
ID gate for tracking holding
Jump prohibition
MN103007BGA(2/4)

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