JVC XV-M565BK Service Manual page 56

XV-M565BK/M567GD
ZIVA3-PEO (IC501) : AV Decoder
1.Pin function
Symbol
I/O
Pin No.
1 I/O
TEST PIN0
2
HDATA0
3 I/O
HDATA1
4
HDATA2
5
E VDD
6 I/O
HDATA3
7
E VSS
8
HDATA4
9
HDATA5
10 I/O
HDATA6
11
HDATA7
12
i vdd
13
RST
14
i vss
15 O
WAIT
16 O
INT
17
E VDD
18
ARAM OE
19
E VSS
20
ARAM WE
21
ARAM DATA0
22
ARAM DATA1
23
ARAM DATA2
24
ARAM DATA3
25
ARAM DATA4
26
ARAM DATA5
27
E VDD
28
ARAM DATA6
29
E VSS
30
ARAM DATA7
31
ARAM ADDR0
32
ARAM ADDR1
33
ARAM ADDR2
34
ARAM ADDR3
35
ARAM ADDR4
36
E VDD
37
ARAM ADDR5
38
E VSS
39
ARAM ADDR6
40
i vdd
41
ARAM ADDR7
42
i vss
1-56
Function
Programmable I/O pins.Input mode after reset.
8-bit bi-derectional host data bus. writes data to the decoder Code FIFO via HDATA.
MSB of the 32-bit word is written first. The host also reads and writes the decoder
internal registers and local SDRAM via HDATA.
- 3.3-V supply voltage for I/O signals.
8-bit bi-derectional host data bus. writes data to the decoder Code FIFO via HDATA.
MSB of the 32-bit word is written first. The host also reads and writes the decoder
internal registers and local SDRAM via HDATA.
- Ground for core logic and I/O signals.
8-bit bi-derectional host data bus. writes data to the decoder Code FIFO via HDATA.
MSB of the 32-bit word is written first. The host also reads and writes the decoder
internal registers and local SDRAM via HDATA.
- 2.5-V supply voltage for core logic.
I Hardware reset. An external device asserts RESET(active LOW) to execute a decoder
hardware reset. To ensure proper initialization after power is stable,assert RESET for at
least 20 ms.
- Ground for core logic and I/O signals.
Transfer not complate / data acknowledge. Active LOW to indicate host initiated transfer
is not complate.WAIT is asserted after the falling edge of CS and reasserted when
decoder is ready to complate transfer cycle. Open drain signal, must be pulled-up via
1kW to 3.3 volts. Driven high for 10 ns before tristate.
Host interrupt. Open drain signal, must be pulled-up via 4.7kW to 3.3 volts.
Driven high for 10 ns before tristate.
- 3.3-V supply voltage for I/O signals.
- Connected to TP540
- Ground for core logic and I/O signals.
- Connected to TP541
Not used
- (Programmable I/O pins. Input mode after reset)
- 3.3-V supply voltage for I/O signals.
- Not used (Programmable I/O pins. Input mode after reset)
- Ground for core logic and I/O signals.
- Not used (Programmable I/O pins. Input mode after reset)
- Connected to TP550
- Connected to TP551
- Connected to TP552
- Connected to TP553
- Connected to TP554
- 3.3-V supply voltage for I/O signals.
- Connected to TP555
- Ground for core logic and I/O signals.
- Connected to TP556
- 2.5-V supply voltage for core logic.
- Connected to TP557
- Ground for core logic and I/O signals.
ZIVA3-PEO (1/5)