JVC XV-M565BK Service Manual page 57

Symbol
I/O
Pin No.
-
43
ARAM ADDR8
-
44
ARAM ADDR9
-
45
ARAM ADDR10
-
46
ARAM ADDR11
-
E VDD
47
-
48
ARAM ADDR12
-
49 E VSS
-
50
ARAM ADDR13
51 -
ARAM ADDR14
52 TEST PIN1
I/O
53 MDATA 15
I/O
54
MDATA 0
I/O
55 E VDD
-
56
MDATA 14
I/O
57 E VSS
-
58 MDATA 1
59
MDATA 13
I/O
60 MDATA 2
61
E VDD
-
62 MDATA 12
I/O
63
E VSS
-
64 MDATA 3
I/O
65 i vdd
-
66
MDATA 11
I/O
67 i vss
-
68
MDATA 4
I/O
69 E VDD
-
70 MDATA 10
I/O
71
E VSS
-
72 MDATA 5
73
MDATA 9
I/O
74 MDATA 6
75 E VDD
-
76
MDATA 8
I/O
77 E VSS
-
78
MDATA 7
I/O
79 LDQM
O
80 UDQM
O
81
E VDD
-
82
O
MWE
83 E VSS
-
84 SD CLK
O
85
SD CAS O
86
O
SD RAS
87
E VDD
-
88
O
SD CS1
89 E VSS
-
90
SD CS0
O
91 i vdd
-
92
EDO CAS -
93 i vss
-
94
-
EDO RAS
95
E VDD
-
96 MADDR 9
O
97
E VSS
-
98 MADDR 11
O
Function
Connected to TP558
Connected to TP559
Connected to TP560
Connected to TP561
3.3-V supply voltage for I/O signals.
Connected to TP562
Ground for core logic and I/O signals.
Connected to TP563
Connected to TP564
Programmable I/O pins. Input mode after reset
Memory data
Memory data
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
2.5-V supply voltage for core logic.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
3.3-V supply voltage for I/O signals.
Memory data.
Ground for core logic and I/O signals.
Memory data.
SDRAM LDQM.
SDRAM UDQM.
3.3-V supply voltage for I/O signals.
SDRAM write enable. Decoder asserts active LOW to request a write operation to the
SDRAM array.
Ground for core logic and I/O signals.
SDRAM system clock.
Active LOW SDRAM column address.
Active LOW SDRAM row address.
3.3-V supply voltage for I/o signals.
Active LOW SDRAM bank select.
Ground for core logic and I/O signals.
Active LOW SDRAM bank select.
2.5-V supply voltage for core logic.
Connected to TP511
Ground for core logic and I/O signals.
Connected to TP512
3.3-V supply voltage for I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
XV-M565BK/M567GD
ZIVA3-PEO (2/5)
1-57