Ddr3 Memory Module - Xilinx KC705 User Manual

Chapter 1: KC705 Evaluation Board Features

DDR3 Memory Module

[Figure
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM)
for storing user code and data.
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The DDR3 interface is implemented across I/O banks 32, 33, and 34. Each bank is a 1.5V
high-performance (HP) bank having a dedicated DCI VRP/N resistor connection. An
external 0.75V reference VTTREF is provided for data interface banks 32 and 34. Any
interface connected to these banks that requires a reference voltage must use this FPGA
voltage reference. The connections between the DDR 3 memory and the FPGA are listed in
Table
Table 1-4: DDR3 Memory Connections to the FPGA
12
1-2, callout 2]
Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
Supply voltage: 1.5V
Datapath width: 64 bits
Data rate: Up to 1,600 MT/s
1-4.
U1 FPGA Pin Net Name
AH12 DDR3_A0
AG13 DDR3_A1
AG12 DDR3_A2
AF12 DDR3_A3
AJ12 DDR3_A4
AJ13 DDR3_A5
AJ14 DDR3_A6
AH14 DDR3_A7
AK13 DDR3_A8
AK14 DDR3_A9
AF13 DDR3_A10
AE13 DDR3_A11
AJ11 DDR3_A12
AH11 DDR3_A13
AK10 DDR3_A14
AK11 DDR3_A15
AH9 DDR3_BA0
AG9 DDR3_BA1
AK9 DDR3_BA2
AA15 DDR3_D0
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J1 DDR3 Memory
Pin Number Pin Name
98 A0
97 A1
96 A2
95 A3
92 A4
91 A5
90 A6
86 A7
89 A8
85 A9
107 A10/AP
84 A11
83 A12_BC_N
119 A13
80 A14
78 A15
109 BA0
108 BA1
79 BA2
5 DQ0
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013