Epson DFX-5000+ Service Manual page 78

Operating Principles
Reset IC PTS591D monitors the +5 VDC line on the Cl 17 MAIN board assembly.
If it drops to 4.2 VDC, the reset IC outputs a LOW signal to the CPU, gate array,
and optional interface board. The gate array outputs the RESET signal to the
reset port ofthe CPU and also to the gate array itself, via the delay control circuit
(CR circuit). The delay control circuit consists of R26 and C72 and controls the
reset timing for the CPU and Type B interface card.
Reset IC M51955 monitors the +35 VDC line. Normally, the dividing resistors
(R27 and R28) input approximately 1.7 VDC to pin 2. When the detection level is
1.7 VDC, the +35 VDC line drops into the 22.9 V to 30.0 V range.
to the CPU's NM1 port. When the printer is turned off, this circuit operates and
manages writing to the EEPROM.
2-26
NMI
Figure 2-20. Reset Circuit Block Diagram
CPU
EPSON DFX-5000+ Service Manual