Contec F&eIT Series User Manual page 63

Using the Memory Address Map
Setting the Clear Signal Synchronization
This item sets the synchronization of the count value clear operation and phase A
signals based on clear signals (phase Z).
- Synchronous clear
If counting direction =01h and clear signal input logic =00h, the counter is zero-
cleared when A phase rises with the B-phase input LOW an the Z-phase input
HIGH; the counting process is started when A phase rises after the Z-phase input
turns LOW.
Phase A
(phase A/UP)
Phase B
(phase B/DOWN)
Phase Z
(phase Z/CLR)
Count value
* If count direction = 00h, a DOWN count commences when phase A rises with phase B being LOW;
if clear signal input logic = 01h, the operation is enabled with the phase Z input is LOW.
Figure 5.6.
- Asynchronous clear
If counting direction =01h and clear signal input logic =00h, the counter is zero-
cleared when Z phase turns HIGH, irrespective of the input state of phase A or B. The
counting process is started at the next rise of the A phase, irrespective of the input
state of Z phase.
Phase A
(phase A/UP)
Phase B
(phase B/DOWN)
Phase Z
(phase Z/CLR)
Count value
* If count direction = 00h, a DOWN count commences when phase A rises with phase B being LOW;
if clear signal input logic = 01h, the operation is enabled with the phase Z input is LOW.
Figure 5.7.
58
00h: Asynchronous clear
01h: Synchronous clear
1 2
Example of a Synchronous Clear Counting Operation
1 2
Example of an Asynchronous Clear Counting Operation
0 1
3
1
0
CNT24-2(FIT)GY