Contec F&eIT Series User Manual page 59

Using the Memory Address Map
- Digital filter value
This item sets a digital filter value.
Digital filter value (h)
Precision: ±1/10000 relative to the cycle settings
The digital filter is designed to cut noise, such as the chattering of A, B, and Z-
phase input signals (a digital filter for generic input signals is not provided). The
value of a digital filter should be selected by considering the frequency of input
signals.
Digital filter values determine the sampling clock cycle for the digital filter. When
detecting 4 clocks of continuous HIGH (or LOW) signals by sampling the input
signals with this sampling clock, the digital filter outputs a HIGH (or a LOW), and
transmits the signal to the counter circuit. As a result, external input signals are read
with a delay of 4 sampling clock cycles.
External input signal
External input signal
Clock circuit input
Figure 5.1.
54
0000 Disabled digital filter (and above)
005E
01A4
0BB8
3A98
Digital filter
Invalid
* Same as the LOW level
Digital Filter
Input frequency
94Hz and above
420Hz and above
3kHz and above
15kHz and above
Input of the counter circuit
4 setup sampling clock cycles
Valid
Sampling clock cycle
0.1µsec
1056.1µsec
236.9µsec
32.1µsec
6.5µsec
CNT24-2(FIT)GY