Contec F&eIT Series User Manual page 34

Synchronous Clear
If DIR=1 and ZSEL=0, the counter is zero-cleared when A phase rises with the B-
phase input LOW an the Z-phase input HIGH; the counting process is started when A
phase rises after the Z-phase input turns LOW.
Phase A
(phase A/UP)
Phase B
(phase B/DOWN)
Phase Z
(phase Z/CLR)
Count value
* If DIR = 0, a DOWN count commences when phase A rises with phase B LOW.
if ZSEL= 1, the operation is enabled when phase Z input is LOW.
Figure 4.13.
Asynchronous Clear
If DIR=1 and ZSEL=0, the counter is zero-cleared when Z phase turns HIGH,
irrespective of the input state of phase A or B. The counting process is started at the
next rise of A phase, irrespective of the input state of Z phase.
Phase A
(phase A/UP)
Phase B
(phase B/DOWN)
Phase Z
(phase Z/CLR)
Count value
* If DIR = 0, a DOWN count commences when phase A rises with phase B LOW.
if ZSEL= 1, the operation is enabled when phase Z input is LOW.
Figure 4.14.
CNT24-2(FIT)GY
1 2
Example of Counting with a Synchronous Clear
1 2
3
Example of Counting with an Asynchronous Clear
Using the I/O Address Map
0 1
0 1
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