Texas Instruments TRF7970A Manual page 24

TRF7970A
SLOS743L – AUGUST 2011 – REVISED MARCH 2017
The framing section also supports bit-collision detection as specified in ISO/IEC 14443 A and
ISO/IEC 15693. When a bit collision is detected, an interrupt request is sent and a flag is set in the IRQ
Status register (0x0C). For ISO/IEC 14443 A specifically, the position of the bit collision is written in two
registers: partly in the Collision Position register (0x0E) and partly in the Collision Position and Interrupt
Mask register (0x0D) (bits B6 and B7).
This collision position is presented as sequential bit number, where the count starts immediately after the
start bit. This means a collision in the first bit of a UID would give the value 00 0001 0000 in these
registers when their contents are combined after being read (the count starts with 0 and the first 16 bits
are the command code and the number of valid bits [NVB] byte).
The receive section also contains two timers.
The RX wait time timer is controlled by the value in the RX Wait Time register (0x08). This timer defines
the time interval after the end of the transmit operation during which the receive decoders are not active
(held in reset state). This prevents false detections resulting from transients following the transmit
operation. The value of the RX Wait Time register (0x08) defines the time in increments of 9.44 µs. This
register is preset at every write to the ISO Control register (0x01) according to the minimum tag response
time defined by each standard.
The RX no response timer is controlled by the RX No Response Wait Time register (0x07). This timer
measures the time from the start of the slot in the anticollision sequence until the start of tag response. If
there is no tag response in the defined time, an interrupt request is sent and a flag is set in the IRQ Status
register (0x0C). This enables the external controller to be relieved of the task of detecting empty slots. The
wait time is stored in the register in increments of 37.76 µs. This register is also preset automatically for
every new protocol selection.
The main register controlling the digital part of the receiver is the ISO Control register (0x01). By writing to
this register, the user selects the protocol to be used. With each new write in this register, all related
registers are preset to their defaults for the protocol, so no further adjustments in other registers are
needed for proper operation.
If changes to other registers are needed to fine-tune the system, those changes must be
made after setting the ISO Control register (0x01).
24 Detailed Description
Table 6-6 describes the bit fields of the ISO Control register (0x01).
NOTE
Submit Documentation Feedback
Product Folder Links:
Copyright © 2011–2017, Texas Instruments Incorporated
TRF7970A
www.ti.com