System Block Diagram; Power Supplies - Texas Instruments TRF7970A Manual

TRF7970A
SLOS743L – AUGUST 2011 – REVISED MARCH 2017
6.1.3.3 Card Emulation
The chip can enter this mode by setting appropriate option bits. The chip can emulate ISO/IEC 14443 A
and B card types. For ISO/IEC 14443 A and B, the emulation supports 106-kbps data rate to start. For
ISO/IEC 14443 A, the anticollision algorithm can be performed using an internal state machine, which
relieves the MCU of any real-time tasks; however, this method can present interoperability challenges with
other NFC devices due to timing requirements. To ensure best interoperability, TI recommends allowing
the MCU to manage the anticollision process, instead. The unique ID required for anticollision is provided
by the MCU after wakeup of the system.
6.2

System Block Diagram

Figure 6-2 shows a block diagram of the TRF7970A.
MUX
RX_IN1
RX_IN2
VDD_PA
TX_OUT
Analog Front End
VSS_PA
EN
EN2
Digital Control
State Machine
ASK/OOK
MOD
OSC_IN
Crystal or Oscillator
Timing System
OSC_OUT
6.3

Power Supplies

The TRF7970A positive supply input V
V , V and V
DD_RF DD_A
be connected as indicated in reference schematics. These regulators provide a high power supply reject
ratio (PSRR) as required for RFID reader systems. All regulators are supplied by V
The regulators are not independent and have common control bits in register 0x0B for output voltage
setting. The regulators can be configured to operate in either automatic or manual mode (register 0x0B,
bit 7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the
highest possible supply voltage for RF output (to ensure maximum RF power output). The manual mode
allows the user to manually configure the regulator settings. For applications in which the TRF7970A may
be subjected to external noise, manually reducing the regulator settings can improve RF performance.
16 Detailed Description
Phase and
Gain
Amplitude
Detector
RF Level
Detector
RSSI
(External)
Phase and
Gain
Amplitude
Detector
ISO
Protocol
Handling
Transmitter
Conversion
CRC and Parity
Figure 6-2. System Block Diagram
(pin 2) sources three internal regulators with output voltages
IN
. All regulators use external bypass capacitors for supply noise filtering and must
DD_X
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Product Folder Links:
RSSI
(AUX)
(Control
Registers and
Command
RSSI
(Main)
Filter
Digitizer
and AGC
Interface
Decoder
Bit 127-Byte
Framing
Framing
Serial
Voltage Supply Regulator Systems
(Supply Regulators and Reference Voltages)
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2011–2017, Texas Instruments Incorporated
TRF7970A
VDD_I/O
I/O_0
Logic
State I/O_1
Control
Logic
I/O_2
I/O_3
I/O_4
Logic)
I/O_5
I/O_6
MCU
I/O_7
IRQ
SYS_CLK
FIFO
DATA_CLK
VIN
VDD_A
BAND_GAP
VSS_A
VDD_RF
VSS_RF
VDD_X
VSS
VSS_D
(pin 2).
IN
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