Texas Instruments TRF7970A Manual page 36

TRF7970A
SLOS743L – AUGUST 2011 – REVISED MARCH 2017
During transmission, the MCU loads the TRF7970A FIFO (or during reception the MCU removes data
from the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile,
the byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if
the number of bytes in the FIFO triggers the watermark levels, which are configured in the Adjustable
FIFO IRQ Levels register (0x14). The default setting is for the interrupt to be triggered when receiving
124 bytes during RX or having 4 bytes remaining during TX. These watermark levels are used so that
MCU can send new data or read the data as necessary. The MCU must also validate the number of data
bytes to be sent, so as to not surpass the value defined in the TX Length Byte registers (0x1D and 0x1E).
The MCU also signals the transmit logic when the last byte of data is sent or was removed from the FIFO
during reception.
Figure 6-13 shows an example of checking the FIFO Status register using SPI with SS.
Figure 6-13. Example of Checking the FIFO Status Register Using SPI With SS
6.10.2 Parallel Interface Mode
In parallel mode, the start condition is generated on the rising edge of the I/O_7 pin while the CLK is high.
This is used to reset the interface logic.
the data, with an 8-bit address word first, followed by data.
Communication is ended by:
• The StopSmpl condition, where a falling edge on the I/O_7 pin is expected while CLK is high.
• The StopCont condition, where the I/O_7 pin must have a successive rising and falling edge while CLK
is low to reset the parallel interface and be ready for the new communication sequence.
• The StopSmpl condition is also used to terminate the direct mode.
CLK
I/O_[7]
I/O_[6:0]
Figure 6-14. Parallel Interface Communication With Simple Stop Condition (StopSmpl)
36 Detailed Description
Figure
Start
Condition
50 ns
a1 [7] d1 [7] a2 [7]
a1 [6:0] d1 [6:0] a2 [6:0]
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6-14, Figure 6-15, and Figure 6-16
d2 [7] aN [7]
d2 [6:0] aN [6:0]
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show the sequence of
StopSmpl
Condition
dN [7]
dN [6:0]