Texas Instruments CC2500 Manual
  1. Manuals
  2. Brands
  3. Texas Instruments Manuals
  4. Transceiver
  5. CC2500
  6. Manual

Texas Instruments CC2500 Manual

Low-cost low-power 2.4 ghz rf transceiver
Hide thumbs Also See for CC2500:
Table of Contents

Advertisement

Quick Links

Download this manual
CC2500
Low-Cost Low-Power 2.4 GHz RF Transceiver

Applications

 2400-2483.5 MHz ISM/SRD band systems
 Consumer electronics
 Wireless game controllers

Product Description

The CC2500 is a low-cost 2.4 GHz transceiver
designed for very low-power wireless appli-
cations. The circuit is intended for the 2400-
2483.5 MHz ISM (Industrial, Scientific and
Medical) and SRD (Short Range Device)
frequency band.
The RF transceiver is integrated with a highly
configurable baseband modem. The modem
supports various modulation formats and has
a configurable data rate up to 500 kBaud.
CC2500 provides extensive hardware support
for packet handling, data buffering, burst
transmissions, clear channel assessment, link
quality indication, and wake-on-radio.
The main operating parameters and the 64-
byte transmit/receive FIFOs of CC2500 can be

Key Features

RF Performance

High sensitivity (–104 dBm at 2.4 kBaud,
1% packet error rate)
Low current consumption (13.3 mA in RX,
250 kBaud, input well above sensitivity
limit)
Programmable output power up to +1 dBm
Excellent receiver selectivity and blocking
performance
Programmable data rate from 1.2 to 500
kBaud
Frequency range: 2400 – 2483.5 MHz

Analog Features

OOK, 2-FSK, GFSK, and MSK supported
Suitable for frequency hopping and multi-
channel systems due to a fast settling
 Wireless audio
 Wireless keyboard and mouse
 RF enabled remote controls
controlled via an SPI interface. In a typical
system, the CC2500 will be used together with
a microcontroller and a few additional passive
components.
frequency synthesizer with 90 us settling
time
Automatic
(AFC) can be used to align the frequency
synthesizer
frequency
Integrated analog temperature sensor

Digital Features

Flexible
systems: On-chip support for sync word
detection, address check, flexible packet
length, and automatic CRC handling
Efficient SPI interface: All registers can be
programmed with one "burst" transfer
Digital RSSI output
Programmable channel filter bandwidth
Programmable
indicator
SWRS040C
CC2500
Frequency
Compensation
to
the
received
support
for
packet
Carrier
Sense
Page 1 of 89
centre
oriented
(CS)

Advertisement

Table of Contents
loading

Related Manuals for Texas Instruments CC2500

Summary of Contents for Texas Instruments CC2500

  • Page 1: Applications

     Wireless game controllers  RF enabled remote controls Product Description The CC2500 is a low-cost 2.4 GHz transceiver controlled via an SPI interface. In a typical system, the CC2500 will be used together with designed for very low-power wireless appli- cations.

  • Page 2: Low-Power Features

    CC2500  Programmable Preamble Quality Indicator General (PQI) for improved protection against false  Few external components: Complete on- sync word detection in random noise chip frequency synthesizer, no external  Support for automatic Clear Channel filters or RF switch needed Assessment (CCA) before transmitting (for ...

  • Page 3: Abbreviations

    CC2500 Abbreviations Abbreviations used in this data sheet are described below. Adjacent Channel Power Most Significant Bit Analog to Digital Converter Minimum Shift Keying Automatic Frequency Offset Compensation Not Applicable Automatic Gain Control Non Return to Zero (Coding) Automatic Meter Reading...

  • Page 4: Table Of Contents

    CC2500 Table of Contents APPLICATIONS ............................1 PRODUCT DESCRIPTION.........................1 KEY FEATURES ............................1 RF P ............................1 ERFORMANCE ............................1 NALOG EATURES ............................1 IGITAL EATURES ...........................2 OWER EATURES ................................2 ENERAL ABBREVIATIONS............................3 TABLE OF CONTENTS ..........................4 ......................6 BSOLUTE AXIMUM ATINGS ........................6 PERATING ONDITIONS .......................6 ENERAL HARACTERISTICS .......................7...
  • Page 5 CC2500 16.3 .........................34 MPLITUDE ODULATION ...........34 ECEIVED IGNAL UALIFIERS AND UALITY NFORMATION 17.1 ........................34 UALIFIER 17.2 (PQT) ...................34 REAMBLE UALITY HRESHOLD 17.3 RSSI..............................34 17.4 (CS)..........................35 ARRIER ENSE 17.5 (CCA) ....................37 LEAR HANNEL SSESSMENT 17.6 (LQI) .......................37 UALITY NDICATOR ................37 ORWARD...

  • Page 6: Absolute Maximum Ratings

    Solder reflow temperature According to IPC/JEDEC J-STD-020D <500 According to JEDEC STD 22, method A114, Human Body Model Table 1: Absolute Maximum Ratings Operating Conditions The CC2500 operating conditions are listed in Table 2 below. Parameter Unit Condition/Note C Operating temperature –40...

  • Page 7: Electrical Specifications

    CC2500 Electrical Specifications Current Consumption Tc = 25C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Parameter Unit Condition/Note Current consumption in Voltage regulator to digital part off, register values retained power down modes (SLEEP state).
  • Page 8 CC2500 Current consumption, 11.1 Transmit mode, –12 dBm output power TX states 15.0 Transmit mode, -6 dBm output power 21.2 Transmit mode, 0 dBm output power 21.5 Transmit mode, +1 dBm output power Table 4: Current Consumption SWRS040C Page 8 of 89...

  • Page 9: Rf Receive Section

    CC2500 RF Receive Section Tc = 25C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Parameter Unit Condition/Note Digital channel filter User programmable. The bandwidth limits are bandwidth proportional to crystal frequency (given values assume a 26.0 MHz crystal).
  • Page 10 CC2500 Parameter Unit Condition/Note 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity –89 Saturation –13 Adjacent channel rejection Desired channel 3 dB above the sensitivity limit. 750...

  • Page 11: Rf Transmit Section

    CC2500 RF Transmit Section Tc = 25C, VDD = 3.0 V, 0 dBm if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Parameter Unit Condition/Note  Differential load 80 + j74 Differential impedance as seen from the RF-port (RF_P and impedance RF_N) towards the antenna.

  • Page 12: Crystal Oscillator

    The RC oscillator contains an error in the calibration calibration routine that statistically occurs in 17.3% of all calibrations performed. The given maximum accuracy figures account for the calibration error. Refer also to the CC2500 Errata Notes. % / C Temperature coefficient +0.4...

  • Page 13: Frequency Synthesizer Characteristics

    CC2500 Frequency Synthesizer Characteristics Tc = 25C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Min figures are given using a 27 MHz crystal. Typ and max figures are given using a 26 MHz crystal.

  • Page 14: Analog Temperature Sensor

    CC2500 Analog Temperature Sensor The characteristics of the analog temperature sensor at 3.0 V supply voltage are listed in Table 10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.

  • Page 15: Pin Configuration

    CC2500 Pin Configuration 20 19 18 17 16 SCLK AVDD SO (GDO1) AVDD GDO2 RF_N DVDD RF_P DCOUPL AVDD Exposed die attach pad Figure 1: Pinout Top View Note: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip.
  • Page 16 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling. NOTE: This pin is intended for use with the CC2500 only. It can not be used to provide supply voltage to other devices. GDO0 Digital I/O Digital output pin for general use: ...

  • Page 17: Circuit Description

    BIAS XOSC RBIAS XOSC_Q1 XOSC_Q2 Figure 2: CC2500 Simplified Block Diagram A simplified block diagram of CC2500 is shown signals to the down-conversion mixers in receive mode. in Figure 2. CC2500 A crystal is to be connected to XOSC_Q1 and features a low-IF receiver.
  • Page 18 CC2500 balun that converts the differential RF signal Crystal on CC2500 to a single-ended RF signal. C121 The crystal oscillator uses an external crystal and C131 are needed for DC blocking. with two loading capacitors (C81 and C101). Together with an appropriate LC network, the See Section 26 on page 50 for details.

  • Page 19: Configuration Overview

    The Gerber files for the CC2500EM reference design ([4]) are available from the TI website. Figure 4: CC2500EM Reference Design ([4]) Configuration Overview CC2500 can be configured to achieve optimum  Packet radio hardware support  performance for many different applications.

  • Page 20: Configuration Software

    Figure 5: Simplified State Diagram with Typical Usage and Current Consumption at 250 kBaud Data Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized) Configuration Software  CC2500 can be configured using the SmartRF After chip reset, all the registers have default  values as shown in the tables in Section 32.

  • Page 21: 10 4-Wire Serial Configuration And Data Interface

    SPI interface are done most significant bit first. When CSn is pulled low, the MCU must wait until CC2500 SO pin goes low before starting to All transactions on the SPI interface start with a header byte containing a R/W bit, a burst transfer the header byte.

  • Page 22: Chip Status Byte

    When the header byte, data byte or, command running. strobe is sent on the SPI interface, the chip status byte is sent by the CC2500 on the SO Bits 6, 5, and 4 comprise the STATE value. pin. The status byte contains key status This value reflects the state of the chip.

  • Page 23: Register Access

    (B) in the header byte. The address bits – A ) set the start address in an The configuration registers of the CC2500 are internal address counter. This counter is located on SPI addresses from 0x00 to 0x2E. incremented by one each new byte (every 8 Table 35 on page 58 lists all configuration clock pulses).

  • Page 24: Command Strobes

    80 ppm. Refer to zero and one data byte. After the data byte a the CC2500 Errata Notes [1] for more details. new header byte is expected; hence, CSn can remain low. The burst access method expects one header byte and then consecutive data 10.4...

  • Page 25: Microcontroller Interface And Pin Configuration

    0. The R/W bit controls whether the Figure 9: Register Access Types 11 Microcontroller Interface and Pin Configuration In a typical system, CC2500 will interface to a 11.2 General Control and Status Pins microcontroller. This microcontroller must be...

  • Page 26: Optional Radio Control Feature

    CSn goes high. restored to its default value (0x7F). 11.3 Optional Radio Control Feature SCLK Function The CC2500 has an optional way of controlling Chip unaffected by SCLK/SI  Generates SPWD strobe the radio, by reusing SI, SCLK and CSn from ...

  • Page 27: Receiver Channel Filter Bandwidth

    The following formula gives the the transmitted signal bandwidth should be relation between the register settings and the maximum 480 kHz – 2·98 kHz, which is 284 channel filter bandwidth: kHz. The CC2500 supports the following channel  filter bandwidths: XOSC  ...

  • Page 28: Byte Synchronization

    See Section 17.2 on page 34 for more details. user-configured 16 or 32 bit sync word. The 15 Packet Handling Hardware Support The CC2500 has built-in hardware support for  One byte address check ...

  • Page 29: Data Whitening

    Data whitening can only be used when transmitting, and de-whitening the data in the PKTCTRL0.CC2400_EN=0 (default). receiver. With CC2500 , this can be done Figure 10: Data Whitening in TX Mode  15.2 Packet Format Length byte or constant programmable...
  • Page 30 When for example a 600-byte packet is to be different length configuration than natively transmitted, the MCU should do the following supported by CC2500 . One should make sure (see also Figure 12): that TX mode is not turned off during the ...

  • Page 31: Packet Filtering In Receive Mode

    15.3 Packet Filtering in Receive Mode receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting). CC2500 supports three different types of packet-filtering: address filtering, maximum 15.3.3 CRC Filtering length filtering and CRC filtering. The filtering of a packet when CRC check fails 15.3.1 Address Filtering...

  • Page 32: Packet Handling In Transmit Mode

    CC2500 options. Refer also to the CC2500 Errata Notes The modulator will first send the programmed number of preamble bytes. If data is available [1]. in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word and 15.4.1 PKTCTRL0.CC2400_EN=0...

  • Page 33: Packet Handling In Firmware

    RX sensitivity. Furthermore, as In both RX and TX one can use one of the GDO explained in Section 10.3 and the CC2500 pins to give an interrupt when a sync word has Errata Notes [1], when using SPI polling there...

  • Page 34: Amplitude Modulation

    17 Received Signal Qualifiers and Link Quality Information CC2500 has several qualifiers that can be used The preamble quality estimator increases an internal counter by one each time a bit is...

  • Page 35: Carrier Sense (Cs)

    CC2500 automatically added to the first byte appended Table 25 provides typical values for the after the data payload. RSSI_offset. The RSSI value read from the RSSI status Figure 13 shows typical plots of RSSI readings register is a 2’s complement number. The...
  • Page 36 CC2500 IOCFGx.GDOx_CFG=14 and in the status MAX_DVGA_GAIN[1:0] register bit PKTSTATUS.CS. Other uses of Carrier Sense include the TX-if- -81.5 CCA function (see Section 17.5 on page 37) -90.5 -78.5 and the optional fast RX termination (see Section 19.7 on page 43).

  • Page 37: Clear Channel Assessment (Cca)

    When the STX or SFSTXON command strobe is given while CC2500 is in the RX state, the TX appended after the payload. The value can also be read from the LQI status register. The...
  • Page 38 CC2500 employs matrix interleaving, which is the end of the packet, so that the total length illustrated Figure on-chip of the data to be interleaved is an even interleaving and de-interleaving buffers are 4 x number.

  • Page 39: Radio Control

    SFTX SFRX IDLE Figure 15: Complete Radio Control State Diagram CC2500 has a built-in state machine that is readable in the MARCSTATE status register. used to switch between different operation This register is primarily for test purposes. states (modes). The change of state is done either by using command strobes or by 19.1...

  • Page 40: Crystal Control

    CSn is taken low before reset is completed the turned on. If the user wants to reset the SO pin will first go high, indicating that the CC2500 after this, it is only necessary to issue crystal oscillator is not stabilized, before going an SRES command strobe.

  • Page 41: Active Modes

    Section 17. After a packet is successfully WOR mode. received the radio controller will then go to the CC2500 can be set up to signal the MCU that a state indicated by the MCSM1.RXOFF_MODE setting. The possible destinations are: packet has been received by using the GDO pins.

  • Page 42: Timing

    Figure 18: Event 0 and Event 1 Relationship RX/TX and TX/RX turnaround times are constant. The calibration time is constant The time from the CC2500 enters SLEEP state 18739 clock periods. Table 28 shows timing in until the next Event 0 is programmed to crystal clock cycles for key state transitions.

  • Page 43: Rx Termination Timer

    (RSSI below threshold). See Section 17.4 on page 35 for details on Carrier Sense. 20 Data FIFO The CC2500 contains two 64 byte FIFOs, one The number of bytes in the RX FIFO and TX FIFO can also be read from the status...

  • Page 44: Frequency Programming

    Figure 20: Example of FIFOs at Threshold Figure 19: FIFO_THR=13 vs. Number of Bytes in FIFO (GDOx_CFG=0x00 in RX and GDOx_CFG=0x02 in TX) 21 Frequency Programming The frequency programming in CC2500 is MDMCFG1.CHANSPC_E registers. The channel designed minimize programming spacing registers are mantissa and exponent needed in a channel-oriented system.

  • Page 45: Vco

    (or channel). The number of XOSC cycles for in lock if the register content is different from completing the PLL calibration is given in 0x3F. Refer also to the CC2500 Errata Notes Table 28 on page 42. [1]. For more robust operation the source code...

  • Page 46: Voltage Regulators

    CC2500 23 Voltage Regulators CC2500 contains several on-chip linear voltage If the chip is programmed to enter power-down mode, (SPWD strobe issued), the power will be regulators, which generate the supply voltage needed low-voltage modules. These turned off after CSn goes high. The power and...
  • Page 47 CC2500 Figure 21: PA_POWER and PATABLE Output power, Current consumption, Default power setting typical [dBm] typical [mA] 0xC6 11.1 Table 30: Output Power and Current Consumption for Default PATABLE Setting Output Power, PATABLE Current Consumption, Typical, +25°C, 3.0 V [dBm]...

  • Page 48: Selectivity

    CC2500 25 Selectivity Figure 22 to Figure 26 show the typical selectivity performance (adjacent and alternate rejection). -0.8 -0.6 -0.4 -0.2 Frequency offset [MHz] Figure 22: Typical Selectivity at 2.4 kBaud. IF Frequency is 273.9 kHz. MDMCFG2.DEM_DCFILT_OFF=1 -0.8 -0.6 -0.4 -0.2...
  • Page 49 CC2500 Frequency offset [MHz] Figure 24: Typical Selectivity at 250 kBaud. IF Frequency is 177.7 kHz. MDMCFG2.DEM_DCFILT_OFF=0 Frequency offset [MHz] Figure 25: Typical Selectivity at 250 kBaud. IF Frequency is 457 kHz. MDMCFG2.DEM_DCFILT_OFF=1 Frequency offse t [MHz] Figure 26: Typical Selectivity at 500 kBaud. IF Frequency is 304.7 kHz.

  • Page 50: Crystal Oscillator

    1 V peak-peak amplitude. reference signal. The reference signal must be connected to the 27 External RF Match The balanced RF input and output of CC2500 circuitry ensures match in both RX and TX mode. share two common pins and are designed for...

  • Page 51: Pcb Layout Recommendations

    The best routing is from with metallization connected to ground using the power line to the decoupling capacitor and then to the CC2500 supply pin. Supply power several vias. filtering is very important. The area under the chip is used for grounding...

  • Page 52: General Purpose / Test Output Control Pins

    CC2500 29 General Purpose / Test Output Control Pins The three digital output pins GDO0, GDO1 and IOCFG0.GDO0_CFG register. The voltage on GDO2 are general control pins configured with then proportional GDO0 IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG temperature. See Section 4.7 on page 14 for and IOCFG2.GDO2_CFG respectively.
  • Page 53 In RX mode, data is set up on the falling edge by CC2500 when GDOx_INV=0. 11 (0x0B) In TX mode, data is sampled by CC2500 on the rising edge of the serial clock when GDOx_INV=0. 12 (0x0C) Serial Synchronous Data Output (DO). Used for synchronous serial mode.

  • Page 54: Asynchronous And Synchronous Serial Operation

    RF communication synchronous serial mode, data is transferred systems. For new systems, it is recommended on a two wire serial interface. The CC2500 to use the built-in packet handling features, as provides a clock that is used to set up new...

  • Page 55: Frequency Hopping And Multi-Channel Systems

    FHSS also combats approximately 570 µs smaller blanking interval multipath fading. than solution 1). CC2500 is highly suited for FHSS or multi- channel systems due to its agile frequency 31.3 Wideband Modulation not Using synthesizer...

  • Page 56: Crystal Drift Compensation

    DC biasing can be achieved in the antenna topology, see Figure Antenna Filter CC2500 Balun T/R switch T/R switch Figure 29. Block Diagram of CC2500 Usage with External Power Amplifier SWRS040C Page 56 of 89...

  • Page 57: Configuration Registers

    Note that the burst bit has registers, listed in Table 35. Many of these different meaning for base addresses above registers are for test purposes only, and need and below 0x2F. not be written for normal operation of CC2500 . Address Strobe Description Name...
  • Page 58 CC2500 Preserved in Details on Address Register Description SLEEP State Page Number 0x00 IOCFG2 GDO2 output pin configuration GDO1 output pin configuration 0x01 IOCFG1 0x02 IOCFG0 GDO0 output pin configuration 0x03 FIFOTHR RX FIFO and TX FIFO thresholds 0x04 SYNC1...
  • Page 59 CC2500 Details on Address Register Description Page Number CC2500 part number 0x30 (0xF0) PARTNUM 0x31 (0xF1) VERSION Current version number 0x32 (0xF2) FREQEST Frequency offset estimate 0x33 (0xF3) Demodulator estimate for Link Quality 0x34 (0xF4) RSSI Received signal strength indication...
  • Page 60 CC2500 Write Read Single byte Burst Single byte Burst +0x00 +0x40 +0x80 +0xC0 0x00 IOCFG2 0x01 IOCFG1 0x02 IOCFG0 0x03 FIFOTHR 0x04 SYNC1 0x05 SYNC0 0x06 PKTLEN 0x07 PKTCTRL1 0x08 PKTCTRL0 0x09 ADDR 0x0A CHANNR 0x0B FSCTRL1 0x0C FSCTRL0 0x0D...

  • Page 61: Configuration Register Details - Registers With Preserved Values In Sleep State

    CC2500 32.1 Configuration Register Details – Registers with Preserved Values in SLEEP State 0x00: IOCFG2 – GDO2 Output Pin Configuration Field Name Reset Description Reserved GDO2_INV Invert output, i.e. select active low (1) / high (0) GDO2_CFG[5:0] 41 (0x29) Default is CHIP_RDYn (see Table 33 on page 53).
  • Page 62 CC2500 0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds Field Name Reset Description Reserved Write 0 for compatibility with possible future extensions FIFO_THR[3:0] 7 (0111) Set the threshold for the TX FIFO and RX FIFO. The threshold is exceeded when the number of bytes in the FIFO is equal to or higher than the threshold value.
  • Page 63 CC2500 0x07: PKTCTRL1 – Packet Automation Control Field Name Reset Description PQT[2:0] 0 (000) Preamble quality estimator threshold. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 8 each time a bit is received that is the same as the last bit.
  • Page 64 CC2500 0x08: PKTCTRL0 – Packet Automation Control Field Name Reset Description Reserved WHITE_DATA Turn data whitening on / off 0: Whitening off 1: Whitening on Data whitening can only be used when PKTCTRL0.CC2400_EN=0 (default). PKT_FORMAT[1:0] 0 (00) Format of RX and TX data...
  • Page 65 CC2500 0x0B: FSCTRL1 – Frequency Synthesizer Control Field Name Reset Description Reserved FREQ_IF[4:0] 15 (0x0F) The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator. ...
  • Page 66 CC2500 0x10: MDMCFG4 – Modem Configuration Field Name Reset Description CHANBW_E[1:0] 2 (10) CHANBW_M[1:0] 0 (00) Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth.  XOSC   channel CHANBW CHANBW )· The default values give 203 kHz channel filter bandwidth, assuming a 26.0 MHz crystal.
  • Page 67 CC2500 0x12: MDMCFG2 – Modem Configuration Field Name Reset Description DEM_DCFILT_OFF Disable digital DC blocking filter before demodulator. 0 = Enable (better sensitivity) 1 = Disable (current optimized). Only for data rates ≤ 250 kBaud The recommended IF frequency changes when the DC ...
  • Page 68 CC2500 0x13: MDMCFG1 – Modem Configuration Field Name Reset Description FEC_EN Enable Forward Error Correction (FEC) with interleaving for packet payload 0 = Disable 1 = Enable (Only supported for fixed packet length mode, i.e. PKTCTRL0.LENGTH_CONFIG=0) NUM_PREAMBLE[2:0] 2 (010) Sets the minimum number of preamble bytes to be transmitted...
  • Page 69 CC2500 0x15: DEVIATN – Modem Deviation Setting Field Name Reset Description Reserved DEVIATION_E[2:0] 4 (100) Deviation exponent Reserved DEVIATION_M[2:0] 7 (111) When MSK modulation is enabled: Sets fraction of symbol period used for phase change. Refer to  the SmartRF Studio software [5] for correct DEVIATN setting when using MSK.
  • Page 70 CC2500 0x16: MCSM2 – Main Radio Control State Machine Configuration Field Name Reset Description Reserved Reserved RX_TIME_RSSI Direct RX termination based on RSSI measurement (carrier sense). RX_TIME_QUAL When the RX_TIME timer expires the chip stays in RX mode if sync word is found when RX_TIME_QUAL=0, or either sync word is found or PQT is set when RX_TIME_QUAL=1.
  • Page 71 CC2500 0x17: MCSM1 – Main Radio Control State Machine Configuration Field Name Reset Description Reserved CCA_MODE[1:0] 3 (11) Selects CCA_MODE; Reflected in CCA signal Setting Clear channel indication 0 (00) Always 1 (01) If RSSI below threshold 2 (10) Unless currently receiving a packet...
  • Page 72 CC2500 0x18: MCSM0 – Main Radio Control State Machine Configuration Field Name Reset Description Reserved FS_AUTOCAL[1:0] 0 (00) Automatically calibrate when going to RX or TX, or back to IDLE Setting When to perform automatic calibration 0 (00) Never (manually calibrate using SCAL strobe)
  • Page 73 CC2500 0x19: FOCCFG – Frequency Offset Compensation Configuration Field Name Reset Description Reserved FOC_BS_CS_GATE If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CARRIER_SENSE signal goes high. FOC_PRE_K[1:0] 2 (10) The frequency compensation loop gain to be used before a sync word is detected.
  • Page 74 CC2500 0x1A: BSCFG – Bit Synchronization Configuration Field Name Reset Description BS_PRE_KI[1:0] 1 (01) The clock recovery feedback loop integral gain to be used before a sync word is detected (used to correct offsets in data rate): Setting Clock recovery loop integral gain before sync word...
  • Page 75 CC2500 0x1B: AGCCTRL2 – AGC Control Field Name Reset Description MAX_DVGA_GAIN[1:0] 0 (00) Reduces the maximum allowable DVGA gain. Setting Allowable DVGA settings 0 (00) All gain settings can be used 1 (01) The highest gain setting can not be used...
  • Page 76 CC2500 0x1C: AGCCTRL1 – AGC Control Field Name Reset Description Reserved AGC_LNA_PRIORITY Selects between two different strategies for LNA and LNA2 gain adjustment. When 1, the LNA gain is decreased first. When 0, the LNA2 gain is decreased to minimum before decreasing LNA gain.
  • Page 77 CC2500 0x1D: AGCCTRL0 – AGC Control Field Name Reset Description HYST_LEVEL[1:0] 2 (10) Sets the level of hysteresis on the magnitude deviation (internal AGC signal that determines gain changes). Setting Description No hysteresis, small symmetric dead zone, 0 (00) high gain...
  • Page 78 CC2500 0x1F: WOREVT0 – Low Byte Event0 Timeout Field Name Reset Description EVENT0[7:0] 107 (0x6B) Low byte of Event 0 timeout register. The default Event 0 value gives 1.0 s timeout, assuming a 26.0 MHz crystal. 0x20: WORCTRL – Wake On Radio Control...
  • Page 79 CC2500 0x22: FREND0 – Front End TX configuration Field Name Reset Description Reserved LODIV_BUF_CURRENT_TX[1:0] 1 (01) Adjusts current TX LO buffer (input to PA). The value to use in  this field is given by the SmartRF Studio software [5].

  • Page 80: Configuration Register Details - Registers That Lose Programming In Sleep State

    CC2500 0x25: FSCAL1 – Frequency Synthesizer Calibration Field Name Reset Description Reserved FSCAL1[5:0] Frequency synthesizer calibration result register. Capacitor array (0x20) setting for VCO coarse tuning. Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values.

  • Page 81: Status Register Details

    CC2500 0x2B: AGCTEST – AGC Test Field Name Reset Description AGCTEST[7:0] For test only. Do not write to this register. (0x3F) 0x2C: TEST2 – Various Test Settings Field Name Reset Description Set to 0x81 for improved sensitivity at data rates ≤100 kBaud. The...
  • Page 82 CC2500 0x33 (0xF3): LQI – Demodulator Estimate for Link Quality Field Name Reset Description CRC_OK The last CRC comparison matched. Cleared when entering/restarting RX mode. Only valid if PKTCTRL0.CC2400_EN=1. LQI_EST[6:0] The Link Quality Indicator estimates how easily a received signal can be demodulated.
  • Page 83 CC2500 0x36 (0xF6): WORTIME1 – High Byte of WOR Time Field Name Reset Description TIME[15:8] High byte of timer value in WOR module 0x37 (0xF7): WORTIME0 – Low Byte of WOR Time Field Name Reset Description TIME[7:0] Low byte of timer value in WOR module 0x38 (0xF8): PKTSTATUS –...
  • Page 84 CC2500 0x3B (0xFB): RXBYTES – Underflow and Number of Bytes Field Name Reset Description RXFIFO_OVERFLOW NUM_RXBYTES Number of bytes in RX FIFO 0x3C (0xFC): RCCTRL1_STATUS – Last RC Oscillator Calibration Result Field Name Reset Description Reserved RCCTRL1_STATUS[6:0] Contains the value from the last run of the RC oscillator calibration routine.

  • Page 85: Package Description (Qfn 20)

    CC2500 33 Package Description (QFN 20) 33.1 Recommended PCB Layout for Package (QFN 20) Figure 30: Recommended PCB Layout for QFN 20 Package Note: The figure is an illustration only and not to scale. There are five 10 mil diameter via holes distributed symmetrically in the ground pad under the package.

  • Page 86: Ordering Information

    CC2500_CC2550 Development Kit CC2500EMK CC1101 Development Kit Figure 31: Ordering Information 35 References [1] CC2500 Errata Notes (swrz002.pdf) [2] AN032 2.4 GHz Regulations (swra060.pdf) [3] AN047 CC1100/CC2500 – Wake-On-Radio (swra126.pdf) [4] CC2500EM Reference Design 1.0 (swrr016.zip) SWRS040C Page 86 of 89...
  • Page 87 CC2500 ® [5] SmartRF Studio (swrc046.zip) [6] CC1100 CC2500 Examples Libraries (swrc021.zip) [7] CC1100/CC1150DK & CC2500/CC2550DK Development Kit Examples & Libraries User Manual (swru109.pdf) [8] CC25XX Folded Dipole Reference Design (swrc065.zip) [9] DN004 Folded Dipole Antenna for CCC25xx (swra118.pdf) SWRS040C...

  • Page 88: General Information

    CC2500 36 General Information 36.1 Document History Revision Date Description/Changes SWRS040C 2008-05-04 Updated package and ordering information. SWRS040B 2007-05-09 kbps replaced by kBaud throughout the document. Some of the sections have been re-written to be easier to read without having any new info added.
  • Page 89 CC2500 Revision Date Description/Changes 2006-06-28 Added figures to table on SPI interface timing requirements. Added information about SPI read. SWRS040A Updates to text and included new figure in section on arbitrary length configuration. Updates to section on CRC check. Added information about CRC check when PKTCTRL0.CC2400_EN=1.
  • Page 90 Op Temp (°C) Device Marking Samples Drawing (4/5) CC2500RGP ACTIVE Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC2500 & no Sb/Br) CC2500RGPR ACTIVE 3000 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC2500 & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
  • Page 91 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2...
  • Page 92 PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) CC2500RGPR 3000 330.0 12.4 12.0 Pack Materials-Page 1...
  • Page 93 PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) CC2500RGPR 3000 350.0 350.0 43.0 Pack Materials-Page 2...
  • Page 96 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated...

Table of Contents