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VCMEM
VRMEM
GNDD
VLMEM
Double
Bounding
pads
BFSR
Baseband
BDR
Serial Port
BFSX
(BSP)
BDX
Clock Gene
CK13M
(CKG)
UDX
MCU
Serial Port
UDR
(USP)
UEN
TMS
Test Access
TCK
Port
TDI
(TAP)
TDO
VCK
Volceband
VFS
Serial Port
VDX
(VSP)
VDR
LEDA
LEDC
Auxlliary
LEDB1
Drivers
LEDB2
(ACD)
GNDL1
GNDL2
ON_nOFF
RESPWONz
CK32K
Voltage
Reference
RPWON
Power
PWON
Control
ITWAKEUP
(VRPC)
TESTRSTz
VREF
REFGND
IBIAS
DBBSCK
SIM CARD
Interface
DBBSIO
(SIM)
DBBSRST
SIMIO
SIMCK
SIMRST
Figure 11. Top lev el block diagram of the IO TA(TW L3025)
VCDBB
VSDBB
VRIO
VRRAM
VRDBB
VCIO
VRSIM
Voltage Regulation
(VREG)
Internal
Bus
Controller
(IBIC)
VBAT
Battery Charger
VBACKUP
Interface
VCHG
(BCI)
ICHG
VCCS
PCHG
VBAT
ICTL
VCHG
VBATS
- 25 -
3. H/W CIRCUIT DESCRIPTION
GNDA
VCABB
VRABB
TESTV
VLRTC
VXRTC
VBACKUP
Backup
VRRTC
(BREG)
UPR
APC
APC
AFC
AFC
DAC
ADAC
TDR
TEN
Timing
TEST1/INT1
Serial Port
TEST2/INT2
(TSP)
TEST3
TEST4
BULIP
BULIM
BULQP
Baseband
BULQM
Codec
BDLIP
(BBC)
BDLIM
BDLQP
BDLQM
EARP
EARN
AUXOP
AUXON
AUXI
Volceband
HSO
Codec
(VBC)
HSMICP
HSMICBIAS
MICIP
MICIN
MICBIAS
GNDAV
Monitoring
ADC
ADIN1
(MADC)
ADIN2
ADIN3
ADIN4
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