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3. H/W CIRCUIT DESCRIPTION
3.4 Digital Baseband(DBB) Processor
13 MHz or 26 MHz TCXO
SLICER
Boot Rom
External
ARM7
Momories
Memory
Protect
1 Mbit
SRAM
1 Mbit
SRAM
1 Mbit
SRAM
1 Mbit
SRAM
Figure 9. Top level block diagram of the Calypso-AMR C035(PD751992GHH)
3.4.1 General Description
CALYPSO is a chip implementing the digital base-band processes of a GSM/GPRS mobile phone.
Thi s chip combines a DSP sub-chip (LEAD2 CPU) with its program and data memories, a Micro
- Controller core with emulation facilities (ARM7TDMIE), internal 8Kb of Boot ROM memory, 4M bit
SRAM memory, a clock squarer cell, several compiled single-port or 2-ports RAM and CMOS
gates.
The chip will fully support the Full-Rate, Enhanced Full-Rate and Half-Rate speech coding.
CALYPSO implements all features for the structural test of the logic (full-SCAN, BIST, PMT, JTAG
bou ndary-SCAN).
DIV-2
13MHz
DPLL & CLKM
WTDOG
MCU top-cdll
MEMIF
B
R
Debug Unit
I
Unit
D
G
ARM7
E
W
r
DMA (4+)
i
t
e
b
u
B
SK API
f
R
cDSP
.
I
S28C128
D
G
E
DSP subchip
JTAG
- 20 -
ENABLE-CK13Mhz
Asywchro mms WAKE_UP
INTH
SPI
GEA
Die ID
RHEA bus
TIMER1
TIMER2
ARMIO
uWIRE
RHEA bus
CRYPT
RIF
INTH
MCSI
32 Khz CRYSTAL
IT Alarm
RTC
CK 32Khz
ULPD
GSM time
TPU
TSP
SIM
PWL
UART
IRDA
PWT
LPG
12C
UART
modem
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