Sdma Controller Top-Level Block Diagram - Texas Instruments OMAP36 Series Technical Reference Manual

SDMA Functional Description
11.4 SDMA Functional Description
The SDMA module provides high-performance data transfers between memories and peripheral devices
with low processor use. A DMA transfer is programmed through a logical DMA channel, which allows the
transfer to be optimally tailored to the requirements of the application.
Figure 11-6 shows the SDMA controller top-level block diagram.
Read port
Data
Priority
queues
11.4.1 Logical Channel Transfer Overview
As Figure 11-6 shows, the SDMA module has one read port and one write port operating independently of
each other. Buffering is provided between the read and write ports through a FIFO queue memory pool
that is shared dynamically between the active logical channels.
• Logical channel synchronization
A logical channel is described as hardware-synchronized when the DMA transfers are triggered by
DMA requests from a hardware device. Alternatively, a logical channel is described as
nonsynchronized when the DMA transfer is triggered by software.
• Logical channel activation
A logical channel becomes active as follows:
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SDMA
Public Version
Figure 11-6. SDMA Controller Top-Level Block Diagram
Request
Port
access
scheduler
Logical channel
HW DMA requests/
High
Low
SW enable bit
prio. prio.
Logical
Logical Channel 0
Logical channel
channel
context 0
scheduler
Each FIFO is
associated to an
active logical
channel
Copyright © 2009–2010, Texas Instruments Incorporated
Request
access
scheduler
activation
High
prio.
channel
scheduler
FIFO pool
manager
C4
C3
C2
C1
FIFO pool
SWPU177N – December 2009 – Revised November 2010
www.ti.com
Write port
Port
Low
Priority
prio.
queues
Logical
Data
dma-006