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MMU Functional Description
The table walking logic automatically writes the TLB entries. The entries can also be manually written,
which is done typically to ensure that the translation of time-critical data accesses is already present in the
TLB so that they execute as fast as possible. The entries must be locked to prevent them from being
overwritten.
15.3.4.1 TLB Entry Format
TLB entries consist of two parts:
•
The CAM part contains the virtual address tag used to determine if a virtual address translation is in
the TLB. The TLB acts like a fully associative cache addressed by the virtual address tag. The CAM
part also contains the section/page size, as well as the preserved and the valid parameters. See the
MMU_CAM
register table for more details.
•
The RAM part contains the address translation that belongs to the virtual address tag as well as the
endianness, element size, and mixed parameters described in
register table for more details.
The valid parameter specifies whether an entry is valid or not. The preserved parameter determines the
behavior of an entry in the event of a TLB flush. If an entry is set as preserved, it is not deleted when a
TLB is flushed, that is when MMU_GFLUSH[0] GLOBALFLUSH is set to 1. Preserved entries must be
deleted manually.
Section 15.3.3.2
Figure 15-17
shows the TLB entry structure.
2678
Memory Management Units
Public Version
Figure 15-16. TLB Entry Lock Mechanism
describes the procedure to delete TLB entries.
Copyright © 2009–2010, Texas Instruments Incorporated
MMU-016
Section
15.3.3.2. See the
SWPU177N – December 2009 – Revised November 2010
www.ti.com
MMU_RAM
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