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Display Subsystem Basic Programming Model
DSI_TX_FIFO_VC_SIZE.VCn_FIFO_SIZE[n = 0, 3]
2
3
4
The total size of TX FIFO is 128*33 bits. Therefore, the sum of all virtual channel FIFO allocation cannot
exceed 128*33 bits.
Table 7-65
indicates the start address of the space in the FIFO.
DSI_TX_FIFO_VC_SIZE.VCx_FIFO_ADD[x = 0, 2]
0
1
2
3
4
There must be no overlap of different VCs spaces.
When the TX FIFO is full:
•
the overflow interrupt (FIFO_TX_OVF_IRQ) is generated. To monitor this interrupt request, users can
read the DSS.DSI_VCn_IRQSTATUS[3] FIFO_TX_OVF_IRQ status bit.
•
there is no L4 interconnect error generated
•
the commands are accepted but the data are not written into the FIFO
To ensure that all writes are correctly stored in the TX FIFO, the FIFO should not be full. The software
must read the room in the space allocated for the VC in the TX FIFO by reading the
DSS.DSI_TX_FIFO_VC_EMPTINESS
VC, the
DSS.DSI_TX_FIFO_VC_EMPTINESS
When waiting to receive the first VSYNC event on the video port to start the video mode on DSI link no
command data from TX FIFO should be sent on the interface. It is required to ensure that when receiving
the VSYNC event, there is no on-going command mode transfer that could delay the start of video mode
on the DSI link.
7.5.4.10.2 Command Mode RX FIFO
The RX FIFO is used to store the data received from the DSI complex I/O. The data are always packed in
the RX FIFO (single or multiple packets receiving during a single or multiple BTA periods).
The read requests access to corresponding VC locations to transfer data for a specific VC. The logic
managing the FIFO must be able to extract 32-bit values in-order for a specific VC upon read requests.
The byte enable of the read access is ignored. Each read returns one 32-bit value from the RX FIFO. If
the application accesses the RX FIFO should extract always 32-bit values. Only in the case of 1, 2, or 3
bytes are remaining in the RX FIFO.
The read requests (single or burst) can be less, equal or greater than the packet size. If the packet size is
smaller than the read request, the following packet(s) is also transferred. If the packet size is longer than
the read request, only part of the packet is transfer. In that case, the logic should keep the VC information
to provide the rest of the data during the next read request(s).
1744
Display Subsystem
Public Version
Table 7-64. Virtual Channel TX FIFO Size Values (continued)
Table 7-65. Virtual Channel TX FIFO Start Address
register. In case there is no space allocated in the TX FIFO for the
Copyright © 2009–2010, Texas Instruments Incorporated
Space Size (up to the size of the FIFO)
64 x 33 bits
96 x 33 bits
128 x 33 bits
Start Address
0
32
64
96
128
CAUTION
register indicates a value of 0 for the VC space emptiness.
SWPU177N – December 2009 – Revised November 2010
www.ti.com
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