Nand Page Mapping And Ecc: Per-Sector Schemes, With Separate Ecc - Texas Instruments OMAP36 Series Technical Reference Manual

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Figure 10-35. NAND Page Mapping and ECC: Per-Sector Schemes, With Separate ECC
M9
Per-sector spares, separate ECC
Spares covered by sector ECC
All ECC at the end
Mode Size0
Write 6 P
Read 5 P
M
Per-sector spares, separate ECC
10
Spares covered by sector ECC
All ECC at the end, left-padded
Mode Size0
Write 6 P
Read 11 P
M
Per-sector spares, separate ECC
11
Spares not covered by ECC
All ECC at the end
Mode Size0
Write 6 0
Read 4 SU
M
Per-sector spares, separate ECC
12
Spares not covered by ECC
All ECC at the end, left-padded
Mode Size0
Write 6 0
Read 9 SU
10.1.5.14.4 Prefetch and Write-Posting Engine
NAND device data access cycles are usually much slower than the MCU system frequency; such NAND
read or write accesses issued by the processor will impact the overall system performance, especially
considering long read or write sequences required for NAND page loading or programming. To minimize
this effect on system performance, the GPMC includes a prefetch and write-posting engine, which can be
used to read from or write to any chip-select location in a buffered manner.
The prefetch and write-posting engine uses an embedded 64 bytes (32 Word16) FIFO to prefetch data
SWPU177N – December 2009 – Revised November 2010
Public Version
Sector data
Data0
Size1
512 bytes
E 0
E 0
Sector data
Data0
Size1
512 bytes
1+E 0
E 0
Sector data
Data0
Size1
512 bytes
U+E 0
E 0
Sector data
Data0
Size1
512 bytes
U+1+E 0
E 0
Copyright © 2009–2010, Texas Instruments Incorporated
Sector data non-ECC spares
Data1 Prot0
512 bytes P
1 0
size0
1 0
size0
Sector data non-ECC spares
Data1 Prot0
512 bytes P
1 0
size0
1 0
size0
Sector data non-ECC spares
Data1 Unprot0
512 bytes U
1
size1
1 inactive
size0
Sector data non-ECC spares
Data1 Unprot0
512 bytes U
1
size1
1 inactive
size0
General-Purpose Memory Controller
ECC
Prot1 Ecc0 Ecc1
P E
1 inactive
size0 size1 size1
1 0
size0 size1 size1
ECC
Prot1 Pad Ecc0 Pad
P 1 E 1
1 inactive
size0 size1 size1
1 i. 0 i.
size0 1 size1 1
ECC
Unprot1 Ecc0 Ecc1
U E
inactive
size1
0
size1 size1
ECC
Unprot1 Pad Ecc0 Pad
U 1 E 1
inactive
size1
0 i.
1 size1 1
Memory Subsystem
E
1
Ecc1
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size1
E
1
Ecc1
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gpmc_035
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