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RESET
DSI_TIMING2[15] LP_RX_TO = 0x1
DSI_TIMING[15] LP_RX_TO = 0x0
IDLE
by software
When the interrupt is generated, the hardware should automatically reset the DSS.DSI_TIMING2[15]
LP_RX_TO bit and then assert ForceTXStopMode in order for the DSI complex I/O to drive LP-11 stop
state. The ForceTXStopMode timer is used to define the minimum duration of LP-11 state. The Stop State
can be longer if there is no activity.
The hardware resets the ForceTXStopMode bit, followed by an internal logic reset except all register
values and TX FIFO content, then resets the DSS.DSI_CTRL[0] IF_EN bit. The software should take
action to recover by resetting the peripheral, for example, if it is not responding. It should wait for the
DSS.DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO and DSS.DSI_CTRL[0] IF_EN bits to be reset
before starting the recovery sequence. The TX FIFO is not flushed (the FIFO is flushed only when
DSS.DSI_VCn_CTRL[0] VC_EN is set to 1).
7.4.3.8
Bus Turnaround
The bus turn-around (BTA) is not automatically sent by default after each packet sent to the display(s). It
is programmable independently for each VC ID. The VC can be enabled when DSS.DSI_VCn_CTRL[6]
BTA_EN bit is set to 1 by software. The software should ensure that, when the BTA is sent to the
peripheral, there is enough time allocated for the response and the BTA from the peripheral to host. For
more information about possible DSI PHY timing adjustments during the turn-around procedure, see
Section
7.5.6.4.3, Turn-Around Request in Transmit Mode, and
Receive Mode. When setting the DSS.DSI_VCn_CTRL[6] BTA_EN bit to 1, one BTA is sent manually to
the peripheral. This manual mode can be used for packets in command or video mode.
Acknowledgment from the peripheral for successful BTA is indicated by asserting the BTA_IRQ interrupt, if
it is enabled in the DSS.DSI_VCn_IRQENABLE[5] BTA_IRQ_EN bit. To monitor the BTA interrupt, the
user should read the DSS.DSI_VCn_IRQSTATUS[5] BTA_IRQ status bit.
The BTA should not be sent when the RX FIFO is not empty. Users should take
care of emptying the RX FIFO before sending BTA to the peripheral. It is to
ensure that when receiving new data from peripheral, all the allocated spaces
for all the VCs are empty.
SWPU177N – December 2009 – Revised November 2010
Public Version
Figure 7-99. Low-Power RX Timer FSM
Timer loaded
DSI_TIMING2[15] LP_RX_TO = 0x0 by software
DSI_TIMING2[15] LP_RX_TO = 0x0 by hardware
CAUTION
Copyright © 2009–2010, Texas Instruments Incorporated
Display Subsystem Functional Description
LP RX timer has completed.
Direction has changed (RX >TX).
Section
7.5.6.4.4,Turn-Around Request in
Timer started
Time-out
LP_RX_TO
interrupt
generation and
ForceTxStopMode
sequence
dss-175
1679
Display Subsystem
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