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Figure 7-39. Data Flow in Command Mode Using the Video Port
VP_CLK
ALWAYS_1_period_of_VP.CLK
VP_PCLK
4_VP.CLK_cycles_for_assertion
VP_STALL
PIXELS #1
VP_DATA[23:0]
DSI link
RGB
Two command modes are available:
•
One line buffer: The data are stored in the line buffer before being sent.
•
Two line buffers: The two lines are used if the word count defined in the
DSS.DSI_VCn_LONG_PACKET_HEADER
buffer is used.
NOTE: In command mode, the video port can only be used in one or two line buffer configuration.
The no-line buffer configuration is not allowed.
The packets can be sent using high-speed or low-speed.
NOTE: The DCS command in the payload can be inserted automatically using the DSI_CTRL[24]
DCS_CMD_ENABLE bit. If TE is used, hardware automatically inserts the DCS Write Start
command for the first packet of the frame transfer and the DCS Write Continue command for
all subsequent packets.
7.2.2.2.3 Burst Mode
When the burst mode is enabled, the video port receives data from the display controller at the pixel clock.
The DSI protocol engine buffers the data in its own line FIFO (double-line buffer of 1024 x 24-bit pixels
maximum). The read speed of the line can be twice the pixel clock to increase the blanking time of the
video mode and to allow command mode traffic to be interleaved during the blanking period. The burst
mode uses a dual-line buffer.
The DSI port can output data from one line buffer while the second one is accessed by the video port. The
two processes are concurrent but they do not access the same line at the same time. The DSI transfer
can start only when the whole video port line is transferred into a line buffer. The switch is controlled by
the VP_HS signal on the video port side and by internal signal on the DSI port indicating that the last data
for the current line has been written into the line buffer.
NOTE: The line buffers are used to store the pixels only. The synchronization codes are not stored
in the line buffers. They must be sent according to the video port timings.
SWPU177N – December 2009 – Revised November 2010
Public Version
1_VP.CLK_cycles_after_risir
PIXELS #2
PIXELS #3
PIXELS #4
PIXELS #5
Buffer
Start as soon
as last data is
received in the
buffer
HS
...
or
LP
register is bigger than the line size; otherwise, one line
Copyright © 2009–2010, Texas Instruments Incorporated
ALWAYS_1_period_of_VP.CLK
4_VP.CLK_cycles_for_assertion
PIXELS #1
Buffer
Start as soon
as last data is
received in the
buffer
HS
...
RGB
or
LP
Display Subsystem Environment
PIXELS #2
PIXELS #3
PIXELS #4
PIXELS #5
HS packet, LP
packet, or LP
HS
or
with no data
LP
Display Subsystem
dss-139
1595
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