Table 4.6.5 Write Compensation Truth Table - Fujitsu M2361A Customer Engineering Manual

(4) Write compensation
When the bit density (BPI) is high on a disk surface, and a read operation
is performed, a peak shift phenomenon appears, which tends to widen the
narrow part of the bit spacing because of mutual magnetic interference of
the bits. When such a phenomenon appears, reading of the data will
deviate from the correct bit spacing, causing errors. The write
compensation circuit measures this peak shift beforehand so the data is
written by shifting the peak in the opposite direction of the peak shift
appearing during the read operation.
The NRZ write data (WTDT) sent from the control unit is clocked by the
positive-going edge of the WTCL signal. It is then synchronized with the
internal one-bit cell clock (CLKA) which is issued from the sync decision
window circuit, comparing the phase difference between WTCL and VF02F by
enabling the Write Gate Control (WGCTL) signal.
The NRZ data synchronized with the internal clock is applied to 2-7
encoder circuit. The output of the 2-7 encoder circuit is applied to
six-bit shift register. Each output of the six-bit shift register is
applied to write compensation circuit and then converted into 2-7 data
pulse train with write compensation according to the truth table (as shown
in Table 4.6.5). The preshift timing of write compensation is defined by
Early (EY), on-Time (OT) and Late (LT) signals.
The block diagram and timing chart are given in Figure 4.6.29 and Figure
4.6.30.
Table 4.6.5 Write Compensation Truth Table
REGISTER STATUS WRITE COMP
ENCWD ESR2
1 1
0 1
0
1
1 1
* 0
Note: EY: Early Pulse
OT: On-Time Pulse
LT: Late Pulse
DT: Data Pulse
4 - 92
ESR5
EY OT
1 0 1
1
1 0
0 0
1
0 0 0
*
* *
B03P-4825-0002A ••• 02
LT
0
0
0
1
*
2-7
DT
1
1
1
1
0