Bios Post Progress Codes; Table 6. Post Progress Codes - Intel M20MYP1UR Integration And Service Manual

Intel® Server System M20MYP1UR System Integration and Service Guide

BIOS POST Progress Codes

Table 6 provides a list of all POST progress codes.
Post Code
(Hex) Nibble
SEC Phase
Upper
01
Lower
Upper
02
Lower
Upper
03
Lower
Upper
04
Lower
Upper
05
Lower
Upper
06
Lower
Intel® Ultra Path Interconnect (Intel® UPI) RC (Fully leverage without platform change)
Upper
A1
Lower
Upper
A3
Lower
Upper
A7
Lower
Upper
A8
Lower
Upper
A9
Lower
Upper
AA
Lower
Upper
AB
Lower

Table 6. POST progress codes

LED 3
(MSB) LED 2 LED 1
0 0 0
0 0 0
0 0 0
0 0 1
0 0 0
0 0 1
0 0 0
0 1 0
0 0 0
0 1 0
0 0 0
0 1 1
1 0 1
0 0 0
1 0 1
0 0 1
1 0 1
0 1 1
1 0 1
1 0 0
1 0 1
1 0 0
1 0 1
1 0 1
1 0 1
1 0 1
LED 0
(LSB)
0
First POST code after CPU reset
1
0
Microcode load begin
0
0
CRAM initialization begin
1
0
PEI cache when disabled
0
0
SEC core at power on begin
1
0
Early CPU initialization during SEC phase.
0
0
Collect info such as SBSP, boot mode, reset type, etc.
1
0
Setup minimum path between SBSP and other sockets
1
0
Topology discovery and route calculation
1
0
Program final route
0
0
Program final IO SAD setting
1
0
Protocol layer and other uncore settings
0
0
Transition links to full speed operation
1
Description
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