Table 78. Mrc Progress Codes; Table 79. Post Progress Codes - Intel H2000WP Technical Manual

®
Intel Server System H2000WP Family TPS
Progress Code
0xB0 Detect DIMM population
0xB1 Set DDR3 frequency
0xB2 Gather remaining SPD data
0xB3 Program registers on the memory controller level
0xB4 Evaluate RAS modes and save rank information
0xB5 Program registers on the channel level
0xB6 Perform the JEDEC defined initialization
sequence
0xB7 Train DDR3 ranks

0x01

0x02

0x03

0x04

0x05
0xB8 Initialize CLTT/OLTT
0xB9 Hardware memory test and init
0xBA Execute software memory init
0xBB Program memory map and interleaving
0xBC Program RAS configuration
0xBF MRC is done
0x01
0x02
0x03
0x04
0x05
0x06
90

Table 78. MRC Progress Codes

Main Sequence

Table 79. POST Progress Codes

Progress Code
SEC Phase
First POST code after CPU reset
Microcode load begin
CRAM initialization begin
Pei Cache When Disabled
SEC Core At Power On Begin
Early CPU initialization during Sec
Phase
Intel order number: G52418-006
Appendix B: POST Code LED Decoder
Subsequences/Subfunctions
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Read DQ/DQS training
Receive Enable training
Write Leveling training
Write DQ/DQS training
DDR channel training done
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Description
Revision 1.6