Program-Control Instructions; Low-Power Control Instructions - Texas Instruments TMS320C3x User Manual

Table 13–4. Program-Control Instructions
Instruction Description
B cond Branch conditionally (standard)
B cond D Branch conditionally (delayed)
BR Branch unconditionally (standard)
BRD Branch unconditionally (delayed)
CALL Call subroutine
CALL cond
Call subroutine conditionally
DB cond Decrement and branch conditionally
(standard)
DB cond D
Decrement and branch conditionally
(delayed)
IACK Interrupt acknowledge

13.1.5 Low-Power Control Instructions

Table 13–5. Low-Power Control Instructions
Instruction Description
IDLE2 Low-power idle
LOPOWER Divide clock by 16
13.1.6 Interlocked-Operations Instructions
The low-power control instruction group consists of three instructions that affect
the low-power modes. The low-power idle (IDLE2) instruction allows extremely
low-power mode. The divide-clock-by-16 (LOPOWER) instruction reduces the
rate of the input clock frequency. The restore-clock-to-regular-speed
(MAXSPEED) instruction causes the resumption of full-speed operation.
Table 13–5 lists the low-power control instructions.
The five interlocked-operations instructions (Table 13–6) support multi-
processor communication and the use of external signals to allow for powerful
synchronization mechanisms. They also ensure the integrity of the communi-
cation and result in a high-speed operation. Refer to Chapter 7 for examples
of the use of interlocked instructions.
Instruction Description
IDLE Idle until interrupt
NOP No operation
RETI cond Return from interrupt conditionally
RETS cond
Return from subroutine conditionally
RPTB Repeat block of instructions
RPTS Repeat single instruction
SWI Software interrupt
TRAP cond
Trap conditionally
Instruction Description
MAXSPEED Restore clock to regular speed
Assembly Language Instructions
Instruction Set
13-5