Read With One Wait State For Iostrb - Texas Instruments TMS320C3x User Manual

External Memory Interface Timing
Figure 9–11.Read With One Wait State for IOSTRB = 0
H3
H1
IOSTRB
XR/W
XA
XD
XRDY
9-22
Figure 9–11 illustrates a read with one wait state when IOSTRB is active, and
Figure 9–12 illustrates a write with one wait state when IOSTRB is active. For
each wait state added, IOSTRB, XR/W, and XA are extended one clock cycle.
Writes hold the data on the bus one additional cycle. The sampling of XRDY
is repeated each cycle.
Read
Extra
cycle