3.10 Program The Lmk04828 Using The Configuration Tab On The Hsdc Pro Software; 3.11 Calibrate The Adc Device On The Evm; Verify The Tsw14J56Evm Switch Settings, Initialize The Jesd204B Link (Cpu_Reset), And Verify Tsw14J56Evm Status Leds; 3.13 Capture Data Using The Hsdp Software - Texas Instruments LM97937EVM R2 User Manual

Setup Procedure
NOTE: If the user configures the EVM with options other than the default register values, different
instructions may be required for selecting the device in HSDC Pro. See the
more details.
4. Enter the ADC sampling rate (Fs) as 370M or the desired sampling rate. This number should be equal
to the actual sampling rate of the device and must be updated if the sampling rate changes.

3.10 Program the LMK04828 Using the Configuration Tab on the HSDC Pro Software

1. Note that selecting the EVM in the ADC select drop-down menu made an additional tab appear in
HSDC Pro. Select the tab in the HSDC Pro software and navigate to the 'Clock Dist' sub-tab.
2. Press the 'Configuration 1' button. Verify that pressing the button changes the state of the LEDs on the
translation card, or that it changes the current draw from the +4-V power supply.

3.11 Calibrate the ADC Device on the EVM

1. With the FTDI SPI GUI open on the PC, navigate to the 'Intro' tab.
2. Set the sampling rate selection switch to appropriately indicate the desired sampling rate.
3. Press the calibrate button to calibrate the ADC.
NOTE: This calibrate button executes a calibration sequence that is required for full performance.
This calibration should be performed at power-up, any time the sampling rate changes, or
after exiting the power-down mode. See the device
regarding the necessary calibration sequence.
3.12 Verify the TSW14J56EVM Switch Settings, Initialize the JESD204B Link
(CPU_RESET), and Verify TSW14J56EVM Status LEDs
1. Observe the switches and jumpers on the TSW14J56EVM and verify that they are in the correct
position. The required switch settings are shown in
2. Press the CPU_RESET button (SW7) on the TSW14J56EVM. This button is used to reset the
JESD204B receiver core in the receiving FPGA and should be pressed after power-up, after changing
the test setup, or after changing particular device configuration registers.
3. Verify the status of the D1 to D8 LEDs on the TSW14J56EVM. See the
information regarding the status LEDs.

3.13 Capture Data Using the HSDP Software

1. Verify that 'LM97937EVM_222' is the selected device.
2. Enter the 'ADC sampling rate (Fs)' as the desired sampling rate. This value must be equal to the
operating sampling rate of the device.
8
List of Tables
Table 1. Default State of LEDs on the TSW14J56EVM
During Typical Operation
LED
D1
D2
D3
D4
D5
D6
D7
D8
FPGA_DONE
Copyright © 2013, Texas Instruments Incorporated
Appendix A
data sheet, SNVS990, for details
Table 4.
Appendix A
Status
Blinking
On
Blinking
On
On
Off
Off
On
On
www.ti.com
for
for more
SLAU542 – December 2013
Submit Documentation Feedback