Appendix A
Device-Specific Information
Block Diagram (NI 6722/6723)
Figure A-3 shows a block diagram of the NI 6722/6723.
x4*
16-Bit ADC
PFI/Trigger
Timing
Digital I/O (8)
*NI 6723 only.
A-6 | ni.com
Figure A-3. NI 6722/6723 Block Diagram
Load DAC
13-Bit DAC
13-Bit DAC
13-Bit DAC
13-Bit DAC
13-Bit DAC
13-Bit DAC
13-Bit DAC
13-Bit DAC
x4*
Update,
Busy
Trigger
Timing I/O
Digital I/O
EEPROM
Power On
Misc
Reset
Analog
Output
Mite
FPGA
Interface
Analog
FIFO
Input
Clear
Analog Output
DMA/IRQ
Timing/Control
Bus
DAQ - STC
Interface
RTSI Bus
Interface
RTSI Bus
Control
PCI
PCI
MITE
Bus
Generic
Interface
Bus
Address/Data
Interface
DMA/IRQ