Static Dio; Digital Waveform Generation (Ni 6731/6733 Only); Do Sample Clock Signal (Ni 6731/6733 Only) - National Instruments 6711 User Manual

Chapter 4 Digital I/O

Static DIO

Each DIO line can be used as a static DI or DO line. You can use static DIO lines to monitor or
control digital signals. Each DIO can be individually configured as a digital input (DI) or digital
output (DO). All samples of static DI lines and updates of DO lines are software-timed.
P0.6 and P0.7 also can control the up/down input of general-purpose Counters 0 and 1,
respectively. The up/down control signals, Counter 0 Up/Down and Counter 1 Up/Down, are
input-only and do not affect the operation of the DIO lines. For more information, refer to
Chapter 5, Counters.
Digital Waveform Generation
(NI 6731/6733 Only)
The NI 6731/6733 can generate digital waveforms. This behavior is also referred to as correlated
DO
digital I/O because there is no dedicated clock source for the digital operation. Refer to the
Sample Clock Signal (NI 6731/6733 Only)
section for a list of possible sources.
The DO waveform generation FIFO stores the digital samples. The NI 6731/6733 can use DMA
transfers to move data from the system memory to the DO waveform generation FIFO. The
DAQ device moves samples from the FIFO to the DIO terminals on each rising or falling edge
Direct
of a clock signal, do/SampleClock. For more information on DMA transfers, refer to the
Memory Access (DMA) Bus Interface.
section of Chapter 9,
You can configure each DIO line to be an input, a static output, or a digital waveform generation
output.

DO Sample Clock Signal (NI 6731/6733 Only)

Use the DO Sample Clock (do/SampleClock) signal to update the DO pins with the next sample
from the DO waveform generation FIFO. Because there is no dedicated internal clock for timed
digital operations, you can use an external signal or one of several internal signals as the
DO Sample Clock. You can correlate digital and analog samples in time by choosing the same
signal as the source of the DO Sample Clock, AI Sample Clock, or DI Sample Clock.
If the DAQ device receives a do/SampleClock when the FIFO is empty, the DAQ device reports
an underflow error to the host software.
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