Pac Counter Register - Motorola MC68HC05T16 Technical Data Manual

PAEN - PAC Enable Bit
1 (set)
0 (clear) –
PAMOD - Pulse Accumulator Mode Bit
1 (set)
0 (clear) –
PAIE - PAC Interrupt Enable Bit
1 (set)
0 (clear) –
This PAIE bit enables interrupt caused by the PAOF bit.
7.1.2

PAC Counter Register

7
Address
$0F
When PAC is disabled (PAEN=0), the counter will be cleared to zero. This ensures the Counter
starts from zero every time it is disabled and enabled.
The Pulse Accumulator Counter is read only and resets to zero a write operation.
MOTOROLA
7-2
– Pulse Accumulator enabled.
Pulse Accumulator disabled. PAC counter register is also cleared.
– Gated time accumulation mode.
External event counting mode.
– PAC overflow Interrupt enabled.
PAC overflow Interrupt disabled.
bit 7 bit 6 bit 5
PAD7 PAD6 PAD5
PULSE ACCUMULATOR
bit 4 bit 3 bit 2
PAD4 PAD3 PAD2
State
bit 1 bit 0
on reset
PAD1 PAD0 0000 0000
MC68HC05T16
TPG