M-Bus During Stop Mode; Pulse Accumulator During Stop Mode; Pwm During Stop Mode; Osd During Stop Mode - Motorola MC68HC05T16 Technical Data Manual

12.1.2
When Stop mode is entered, the internal clock driving the M-Bus module will be held at a static
state, thus disabling the operation of the M-Bus module. The M-Bus module hence cannot wake
up the CPU.
12.1.3
When Stop mode is entered, the internal clock driving the Pulse Accumulator module will be held
at a static state, thus disabling the operation of the Pulse Accumulator module. The Pulse
Accumulator module hence cannot wake up the CPU.
12.1.4
When Stop mode is entered, the internal clock driving the PWM module will be held at a static
state, thus disabling the operation of the PWM module. The PWM module hence cannot wake up
the CPU.
12.1.5
When Stop mode is entered, the internal clock driving most of the OSD logic will be held at a static
state, disabling the operation of the OSD module. If the PLL is not stopped by clearing PLLEN bit,
the OSD pixel clock will still run, causing power consumption in Stop mode. The OSD module
cannot wake up the CPU when in Stop mode.
12.1.6
The ADC module operates with the presence of the internal clock, therefore, in Stop mode, ADC
operation is halted.
12
12.1.7
The COP watchdog system stops counting in Stop mode. It continues counting again after 4069
bus cycles when the exit is caused by a external interrupt on IRQ. If exit from Stop mode was
caused by a reset, the MCU will be initialized and the COP watchdog system will be disabled.
MOTOROLA
12-2

M-Bus during Stop Mode

Pulse Accumulator during Stop Mode

PWM during Stop Mode

OSD during Stop Mode

ADC during Stop Mode

COP during Stop Mode

LOW POWER MODES
TPG
MC68HC05T16