Philips 32PF9968/10 Service Manual page 150

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EN 150 9. Q523.1U LA
9.7.2 Full-HD sets @ 60 / 120 Hz
In full-HD sets @ 60 Hz, the output signal coming from the
PNX85xx is fed to the PACIFIC3 via a single LVDS connection.
In full-HD sets @ 120 Hz, the YUV output signal coming from
the PNX85xx is fed to the CYCLONE II FPGA and then
connected to the PACIFIC 3 via a double LVDS connector. The
CYCLONE II FPGA drives the AmbiLight units via I
PACIFIC 3 also generates the pulse-width modulated signal
needed for the "Dimming Backlight" feature, which ensures
additional motion sharpness. As some displays require an
analog signal to switch the LCD, a multiplexer is added to
PNX85xx
M2
MIPS StdBy
Circuit Descriptions, Abbreviation List, and IC Data Sheets
2
C. The
TV520/30 – fHD 50/60/100/120Hz
LVDS
MOP2K7-
LVDS
YUV
Cyclone II
10b
Flash
Select-AnaPWM Dimming
I2C-Scanning (no dimming)
PWM Boost
Figure 9-16 Block diagram display control Full-HD sets 60 / 120 Hz
transform the pulse-width modulated signal. An additional
signal, coming from the PNX85x, makes the selection between
analog and pulse-width modulation, depending on which
display is used. Scanning Backlight displays require an analog
signal, and all other displays a pulse-width modulated. The
signal for "Scanning Backlight" is an I
PNX85xx.
Refer to figure "Block diagram display control Full-HD sets 60 /
120 Hz".
10 b
Debugging only !!
60Hz
JUM
PERS
120Hz
Pacific 3
SPI-flash
M25P05-AVMN6P
9322 206 45668
I2C-Ambi
PWM
Dimming
Converter
+
MUX
Converter
2
C signal coming from the
LVDS
10b
LVDS
fHD
fHD DF
with DFI
MUX
+
AmbiLight
Level
shift
Scanning
Analog (PWM)
Dimming
Backlight
PWM (Analog )
Dimming
Display
Analog Boost Supply
H_16770_128.eps
130707