Philips 32PF9968/10 Service Manual page 148

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EN 148 9. Q523.1U LA
The Analog Audio Front-End Input (AAFE) block is used to
capture Baseband Audio Inputs.
The Sony/Philips Digital Interface (SPDIF) input is used to get
compressed data into the system memory. The multiplexer in
front of the block allows two possible sources of SPDIF signals.
The SPDIF Output is used to generate either PCM data or a
compliant IEC-61937 compressed stream containing MPEG/
Dolby Digital format.
The Audio Input (AI) block is used to transfer stereo audio (I
channel) from the Audio DSP into the system memory for "lip-
sync" delay.
The Audio Output (AO) block supports output of up to four
2
stereo I S channels. The AO is used to transfer data from the
system memory to the Audio DSP, for post processing of the
signal at a sampling frequency of 48 kHz (max.).
Demodulation & Decoding DSP is used for demodulation and
decoding of all analog terrestrial TV sound standards that the
TV520 platform covers.
The Audio Post-Processing DSP supports DPLII together with
volume and tone control, spatializers, and equalizers for 6
channels (max.)
PNX85xx
I2C-3 I2C-DMA3
I2C-2 I2C-DMA2
I2C-1 I2C-Slave
2-wire
2-wire
E-JTAG
Circuit Descriptions, Abbreviation List, and IC Data Sheets
UART1
UART2
E-JTAG
DMA
Figure 9-14 Control and compute subsystem
Digital Audio Decoder DSP is used to decode digital
compressed streams such as MPEG and AC-3. This runs as
SW Codecs on the AV-DSP.
9.6.3 Audio-Video Codec Subsystem
The AV Codec subsystem consists of the modules required to
capture and de-scramble Transport stream inputs together with
decoding of Audio/video Streams. Refer to figure "PNX85xx
video flow diagram" for a clarification.
2
S The sub-system consists of the following modules:
The Conditional Access Interface block provides a direct
interface towards a PCMCIA socket for Conditional Access. It
supports both the DVB CI-CA Specification and the CableCard
(POD) Interface.
The MPEG System Processor (VMSP) provides parsing an
MPEG-2 transport stream, including de-scrambling, de-
multiplexing and appropriate routing of data to the memory.
The Video MPEG Decoder (VMPG) performs MPEG2
decoding for both MP@ML and MP@HL streams.
9.6.4 Control and Compute Subsystem
Refer to figure "Control and compute subsystem" for a
clarification of the blocks that are used in this device.
DDR2-SDRAM
MCU
MIPS
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I2C-4
System
UART-3
Controller
PWM's
80C51
GPIO's
PCI/XIO
PCI/XIO
CAI
CA
H_16770_126.eps
130707