Table of Contents
Advertisement
count).
This subtest operates as follows:
1.
Run timer 1 for 10 seconds.
2.
Every second, print number of seconds remaining
(countdown).
3.
Check to see that Counter 2 matches the number of
interrupts received.
Subtest 3 programs timer 0.
1.
Take 6,000 interrupts.
2.
Reset timer between each interrupt.
Errors
Test 4 can return the following errors:
Stray interrupt from fast clock.
No interrupt generated by the fast clock.
Stray interrupt from slow clock.
N ticks missed.
N more clock interrupts processed than count ticks (N/2)
recorded.
Test Out-put.
Output for a run of the clock test is as follows:
CLOCK TEST
Subtest 1 - Timer 0 TEST
Subtest 2 - Timer l/Counter 2 TEST
9 8 7 6 5 4 3 2 1
Subtest 3 - Timer 0/8259 TEST
TEST 5:
USER I/O ERROR TEST (u)
The user input/output error test makes sure that neither the
external processor registers nor input/output registers, located
in the input/output space (all virtual memory above 4 Mbytes),
can be accessed in user mode.
registers in user mode should generate an exception.
also verifies that the general status register (GSR) and the bus
status registers (BSR's) are set correctly.
Subtest 3 operates as follows:
Any attempt to access these
Tests and Subtests
This test
The subtests are
2-7
Advertisement
Table of Contents
