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register to "not valid" and then tries to write, read, and
execute.
Each of these attempts should generate a bus error, and
the tests verify that a page fault returns.
operation aborts, and an error message returns.
1.
Test page faults caused by reading and writing.
2.
Test page faults caused by trying to execute.
Subtest 1 sets the page table entry to "not valid" and tries to
read and write to the mapped memory.
table entry to "not valid" and tries to execute that page.
Errors
Test 2 can return the following errors:
Page fault does not occur when reads nonmapped page.
Page fault does not occur when executes nonmapped page.
No page fault received on write.
No page fault received on read.
Write/Read-back not continued properly.
No page fault received on execution test.
Page fault when none expected.
Test Output
Output for a run of the page fault test is as follows:
PAGE FAULT TEST
PAGE FAULT SUBTEST 1, Read/Write test
PAGE FAULT TEST
PAGE FAULT SUBTEST 2, Execution test
TEST 3:
PARITY TEST (r)
The parity test checks the parity logic and makes sure that the
processor, bus status registers (BSR's), and the general status
register (GSR) handle exceptions correctly.
subtests are
1.
Reads a parity error through memory to check the BSR.
2.
Execution of a parity error.
Subtest 1 forces a parity error at every memory address and takes
the interrupt, thus forcing all addresses through the BSR.
Subtest 2 writes an instruction containing a parity error to
memory and tries to execute it.
Tests and Subtests
If not, the
The subtests are
Subtest 2 sets the page
The parity test
2-5
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